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H5DU5182ETR-FAC Datasheet(PDF) 18 Page - Hynix Semiconductor

Part # H5DU5182ETR-FAC
Description  512Mb DDR SDRAM
Download  29 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5DU5182ETR-FAC Datasheet(HTML) 18 Page - Hynix Semiconductor

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Rev. 1.0 / Nov. 2009
18
1H5DU5182ETR
H5DU5162ETR
5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temper-
ature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum dif-
ference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum
pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.
6. V
IN=0 to VDD, All other pins are not tested under VIN =0V.
7. DQs are disabled, V
OUT=0 to VDDQ
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Test Conditions
Test Condition
Symbol
Operating Current:
One bank; Active - Precharge; t
RC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing once per clock cycle
I
DD0
Operating Current:
One bank; Active - Read - Precharge;
Burst Length=2; t
RC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock
cycle
I
DD1
Precharge Power Down Standby Current:
All banks idle; Power down mode; CKE=Low, t
CK=tCK(min)
I
DD2P
Idle Standby Current:
/CS=High, All banks idle; t
CK=tCK(min);
CKE=High; address and control inputs changing once per clock cycle.
V
IN=VREF for DQ, DQS and DM
I
DD2F
Idle Quiet Standby Current:
/CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses and other control inputs stable, Vin=Vref
for DQ, DQS and DM
I
DD2Q
Active Power Down Standby Current:
One bank active; Power down mode; CKE=Low, t
CK=tCK(min)
I
DD3P
Active Standby Current:
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge; t
RC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing
once per clock cycle
I
DD3N
Operating Current:
Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per
clock cycle; t
CK=tCK(min); IOUT=0mA
I
DD4R
Operating Current:
Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per
clock cycle; t
CK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle
I
DD4W
Auto Refresh Current:
t
RC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
t
RC=tRFC(min) - 14*tCK for DDR400 at 200Mhz
I
DD5
Self Refresh Current:
CKE =< 0.2V; External clock on; t
CK=tCK(min)
I
DD6
Operating Current - Four Bank Operation:
Four bank interleaving with BL=4, Refer to the following page for detailed test condition
I
DD7


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