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H5DU2562GTR Datasheet(PDF) 3 Page - Hynix Semiconductor

Part No. H5DU2562GTR
Description  256Mb DDR SDRAM
Download  28 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5DU2562GTR Datasheet(HTML) 3 Page - Hynix Semiconductor

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Rev. 1.1 / Sep. 2009
3
H5DU2562GTR
H5DU2582GTR
DESCRIPTION
The H5DU2582GTR and H5DU2562GTR are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ide-
ally suited for the main memory applications which requires large memory density and high bandwidth.
This Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
•VDD, VDDQ = 2.5V +/- 0.2V
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
Programmable CAS latency 2/2.5 (DDR200, 266,
333), 3 (DDR400) and 4 (DDR500) supported
Programmable burst length 2/4/8 with both sequen-
tial and interleave mode
Internal four bank operations with single pulsed
/RAS
Auto refresh and self refresh supported
tRAS lock out function supported
8192 refresh cycles/64ms
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
This product is in compliance with the direc-
tive pertaining of RoHS.
ORDERING INFORMATION
* X means speed grade
Part No.
Configuration
Package
H5DU2582GTR-XXC
32Mx8
400mil
66pin
TSOP-II
H5DU2562GTR-XXC
16Mx16
OPERATING FREQUENCY
Grade
Clock Rate
Remark
(CL-tRCD-tRP)
- FA
250MHz@CL4
DDR500 (4-4-4)
- E3
200MHz@CL3, 166MHz@CL2.5,
133MHz@CL2
DDR400 (3-3-3), DDR333
(2.5-3-3), DDR266 (2-3-3)
- J3
166MHz@CL2.5, 133MHz@CL2 DDR333 (2.5-3-3)
- K2
133MHz@CL2, 133MHz@CL2.5 DDR266A (2-3-3)
- K3
133MHz@CL2.5, 100MHz@CL2 DDR266B (2.5-3-3)
- L2
100MHz@CL2
DDR200 (2-2-2)
*ROHS (Restriction Of Hazardous Substances)


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