H5DU2562GTR datasheet(22/28 Pages) HYNIX

Part #	H5DU2562GTR

Description	256Mb DDR SDRAM

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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22 / 28 page

Rev. 1.1 / Sep. 2009

22

H5DU2562GTR

H5DU2582GTR

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Parameter

Symbol

DDR500

DDR400B

DDR333

DDR266A

DDR266B UN

IT

Min Max Min Max Min Max Min Max Min Max

Data-out high-impedance window

from CK,/CK10

tHZ

-0.65 0.65 -0.7

0.7

-0.7

0.7 -0.75 0.75 -0.75 0.75

ns

Data-out low-impedance window

from CK, /CK10

tLZ

-0.65 0.65 -0.7

0.7

-0.7

0.7 -0.75 0.75 -0.75 0.75

ns

Input Setup Time (fast slew

rate)14,16-18

tIS

0.6

-

0.6

-

0.75

-

0.9

-

0.9

-

ns

Input Hold Time (fast slew

rate)14,16-18

tIH

0.6

-

0.6

-

0.75

-

0.9

-

0.9

-

ns

Input Setup Time (slow slew

rate)15-18

tIS

0.6

-

0.7

-

0.8

-

1.0

-

1.0

-

ns

Input Hold Time (slow slew

rate)15-18

tIH

0.6

-

0.7

-

0.8

-

1.0

-

1.0

-

ns

Input Pulse Width17

tIPW

2.2

-

2.2

-

2.2

-

2.2

-

2.2

-

ns

Write DQS High Level Width

tDQSH 0.35

-

0.35

-

0.35

-

0.35

-

0.35

-

tCK

Write DQS Low Level Width

tDQSL

0.35

-

0.35

-

0.35

-

0.35

-

0.35

-

tCK

Clock to First Rising edge of DQS-

In

tDQSS

0.72 1.25 0.72 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK

DQS falling edge to CK setup time

tDSS

0.2

-

0.2

-0.2

-tCK

DQS falling edge hold time from

CK

tDSH

0.2

-

0.2

-0.2

-tCK

DQ & DM input setup time25

tDS

0.4

-

0.4

-

0.45

-

0.5

-

0.5

-

ns

DQ & DM input hold time25

tDH

0.4

-

0.4

-

0.45

-

0.5

-

0.5

-

ns

DQ & DM Input Pulse Width17

tDIPW

1.6

-

1.75

-

1.75

-

1.75

-

1.75

-

ns

Read DQS Preamble Time

tRPRE

0.9

1.1

0.9

1.1

0.9

1.1

0.9

1.1

0.9

1.1

tCK

Read DQS Postamble Time

tRPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

Write DQS Preamble Setup Time12 tWPRES

0

-

0

-0

-

0

-

0

-

ns

Write DQS Preamble Hold Time

tWPREH 0.25

-

0.25

-

0.25

-

0.25

-

0.25

-

tCK

Write DQS Postamble Time11

tWPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

Mode Register Set Delay

tMRD

2

-

2

-2

-

2

-

2

-

tCK

Exit Self Refresh to non-Read

command23

tXSNR

75

-

75

-75

-

75

-

75

-

ns

Exit Self Refresh to Read

command

tXSRD

200

-

200

-

200

-

200

-

200

-

tCK

Average Periodic Refresh

Interval13,25

tREFI

-

7.8

-

7.8

-

7.8

-

7.8

-

7.8

us

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