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HY5DU12422C Datasheet(PDF) 19 Page - Hynix Semiconductor

Part # HY5DU12422C
Description  512Mb DDR SDRAM
Download  31 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HY5DU12422C Datasheet(HTML) 19 Page - Hynix Semiconductor

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Rev. 1.5 / July 2006
19
1
HY5DU12422C(L)FP
HY5DU12822C(L)FP
HY5DU121622C(L)FP
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Test Conditions
Test Condition
Symbol
Operating Current:
One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock
cycle; address and control inputs changing once per clock cycle
IDD0
Operating Current:
One bank; Active - Read - Precharge;
Burst Length=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle
IDD1
Precharge Power Down Standby Current:
All banks idle; Power down mode; CKE=Low, tCK=tCK(min)
IDD2P
Idle Standby Current:
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM
IDD2N
Idle Standby Current:
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing once per clock cycle.
VIN=VREF for DQ, DQS and DM
IDD2F
Idle Quiet Standby Current:
/CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses and other control inputs stable, Vin=Vref for DQ, DQS
and DM
IDD2Q
Active Power Down Standby Current:
One bank active; Power down mode; CKE=Low, tCK=tCK(min)
IDD3P
Active Standby Current:
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock
cycle
IDD3N
Operating Current:
Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
IDD4R
Operating Current:
Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle
IDD4W
Auto Refresh Current:
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh
tRC=tRFC(min) - 12*tCK for DDR333 at 166Mhz, 14*tCK for DDR400 at 200Mhz
IDD5
Self Refresh Current:
CKE =< 0.2V; External clock on; tCK=tCK(min)
IDD6
Operating Current - Four Bank Operation:
Four bank interleaving with BL=4, Refer to the following page for detailed test condition
IDD7


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