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HYMD264M646BLF8-D43 Datasheet(PDF) 10 Page - Hynix Semiconductor |
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HYMD264M646BLF8-D43 Datasheet(HTML) 10 Page - Hynix Semiconductor |
10 / 17 page HYMD264M646B(L)F8-D43/D4 Rev. 0.2 / Apr. 2004 10 AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol D43(3-3-3) D4(3-4-4) Unit Note Min Max Min Max Row Cycle Time tRC 55 - 58 - ns Auto Refresh Row Cycle Time tRFC 70 - 70 - ns Row Active Time tRAS 40 70K 40 70K ns Active to Read with Auto Precharge Delay tRAP tRCD or tRASmin - tRCD or tRASmin -ns 16 Row Address to Column Address Delay tRCD 15 - 18 - ns Row Active to Row Active Delay tRRD 10 - 10 - ns Column Address to Column Address Delay tCCD 1- 1 - CK Row Precharge Time tRP 15 - 18 - ns Write Recovery Time tWR 15 - 15 - ns Write to Read Command Delay tWTR 2- 2 - CK Auto Precharge Write Recovery + Precharge Time tDAL (tWR/tCK) + (tRP/tCK) - (tWR/tCK) + (tRP/tCK) -CK 15 System Clock Cycle Time CL = 3 tCK 5 10 5 10 ns CL = 2.5 6 12 6 12 ns Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK Data-Out edge to Clock edge Skew tAC -0.7 0.7 -0.7 0.7 ns DQS-Out edge to Clock edge Skew tDQSCK -0.55 0.55 -0.55 0.55 ns DQS-Out edge to Data-Out edge Skew tDQSQ -0.4 -0.4 ns Data-Out hold time from DQS tQH tHP -tQHS - tHP -tQHS -ns 1, 10 Clock Half Period tHP min (tCL,tCH) - min (tCL,tCH) -ns 1,9 Data Hold Skew Factor tQHS -0.5 -0.5 ns 10 Valid Data Output Window tDV tQH-tDQSQ tQH-tDQSQ ns Data-out high-impedance window from CK, /CK tHZ - tAC (Max) - tAC (Max) ns 17 Data-out low-impedance window from CK, /CK tLZ tAC(Min) tAC(Max) tAC(Min) tAC(Max) ns 17 Input Setup Time (fast slew rate) tIS 0.6 - 0.6 - ns 2,3,5,6 Input Hold Time (fast slew rate) tIH 0.6 - 0.6 - ns 2,3,5,6 Input Setup Time (slow slew rate) tIS 0.7 - 0.7 - ns 2,4,5,6 Input Hold Time (slow slew rate) tIH 0.7 - 0.7 - ns 2,4,5,6 Input Pulse Width tIPW 2.2 2.2 ns 6 |
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