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HMT41GV7AMR4C-H9 Datasheet(PDF) 4 Page - Hynix Semiconductor |
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HMT41GV7AMR4C-H9 Datasheet(HTML) 4 Page - Hynix Semiconductor |
4 / 35 page Rev. 0.02 / Apr. 2009 4 1. Description This Hynix DDR3 VLP (Very Low Profile) registered Dual In-Line Memory Module (DIMM) series consists of 2Gb A gen- eration. These are intended for use as main memory in server and workstation systems, providing a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. 1.1 Device Features & Ordering Information 1.1.1 Features 1.1.2 Ordering Information *Please Contact local sales administrator for more details of part number Part Name Density Organizatio n # of DRAMs # of ranks Materials FDHS HMT325V7AFR8C-G7/H9 2GB 256Mx72 9 1 Halogen free X HMT351V7AFR8C-G7/H9 4GB 512Mx72 18 2 Halogen free X HMT351V7AFR4C-G7/H9 4GB 512Mx72 18 1 Halogen free X HMT41GV7AMR8C-G7/H9 8GB 1Gx72 36 4 Halogen free O HMT41GV7AMR4C-G7/H9 8GB 1Gx72 36 2 Halogen free O • VDD=VDDQ=1.5V • VDDSPD=3.3V to 3.6V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and /DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported • Programmableadditivelatency0,CL-1,andCL-2sup ported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks • 8K refresh cycles /64ms • DDR3 SDRAM Package: JEDEC standard 78ball FBGA(x4/x8) with support balls • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • Auto Self Refresh supported • 8 bit pre-fetch • SPD with Integrated TS of Class B |
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