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P89LPC9151 Datasheet(PDF) 2 Page - NXP Semiconductors |
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P89LPC9151 Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 91 page P89LPC9151_61_71_2 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 9 February 2010 2 of 91 NXP Semiconductors P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC 2.2 Additional features A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. In-Application Programming (IAP-Lite) and byte erase allows code memory to be used for non-volatile data storage. Serial flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. Watchdog timer with separate on-chip oscillator, nominal 400 kHz, calibrated to ±5 %, requiring no external components. The watchdog prescaler is selectable from eight values. High-accuracy internal RC oscillator option, with clock doubler option, allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable. Clock switching on the fly among internal RC oscillator, watchdog oscillator, external clock input provides optimal support of minimal power active mode with fast switching to maximum performance. Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1 μA (total power-down with voltage comparators disabled). Active-LOW reset. On-chip power-on reset allows operation without external reset components. A software reset function is also available. Configurable on-chip oscillator with frequency range options selected by user programmed flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz. Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function. Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. High current sourcing/sinking (20 mA) at 4 I/O pins on the P89LPC9151, 3 I/O pins on the P89LPC9161 and 5 I/O pins on the P89LPC9171. All other port pins have high sinking capability (20 mA). A maximum limit is specified for the entire chip. Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. Only power and ground connections are required to operate the P89LPC9151/9161/9171 when internal reset option is selected. Four interrupt priority levels. Five/six keypad interrupt inputs, plus two additional external interrupt inputs. Schmitt trigger port inputs. Second data pointer. Emulation support. |
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