Rev. 1.1 / May. 2005

1

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

184pin Registered DDR SDRAM DIMMs based on 256Mb D ver. (TSOP)

FEATURES

ADDRESS TABLE

Organization

Ranks

SDRAMs

# of

DRAMs

# of row/bank/column Address

Refresh

Method

256MB

32M x 72

1

32Mb x 8

9

13(A0~A12)/2(BA0,BA1)/10(A0~A9)

8K / 64ms

512MB

64M x 72

1

64Mb x 4

18

13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)

8K / 64ms

512MB

64M x 72

2

32Mb x 8

18

13(A0~A12)/2(BA0,BA1)/10(A0~A9)

8K / 64ms

1GB

128M x 72

2

128Mb x 4 (Stacked)

36

13(A0~A12)/2(BA0,BA1)/12(A0~A9,A11,A12) 8K / 64ms

PERFORMANCE RANGE

Part-Number Suffix

-K

-H

-L

Unit

Speed Bin

DDR266A

DDR266B

DDR200

-

CL - tRCD- tRP

2-3-3

2.5-3-3

2-2-2

CK

Max Clock

Frequency

CL=3

---

MHz

CL=2.5

133

133

100

MHz

CL=2

133

133

100

MHz

This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 256Mb D ver. DDR SDRAMs in 400mil.

TSOP II packages on a 184pin glass-epoxy substrate. This Hynix 256Mb D ver. based Registered DIMM series provide

a high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange

and addition.

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JEDEC Standard 184-pin dual in-line memory module

(DIMM)

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Two ranks 128M x 72, 64M x 72 and One rank 64M x

72, 32M x 72 organization

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Error Check Correction (ECC) Capability

DDR333 and below

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All inputs and outputs are compatible with SSTL_2

interface

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Fully differential clock operations (CK & /CK) with

100/133MHz

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DLL aligns DQ and DQS transition with CK transition

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Programmable CAS Latency : DDR200(2 clock),

DDR266(2, 2.5 clock)

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Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

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Edge-aligned DQS with data outs and Center-aligned

DQS with data inputs

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Auto refresh and self refresh supported

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8192refresh cycles / 64ms

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Serial Presence Detect (SPD) with EEPROM

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Built with 256Mb DDR SDRAMs in 400 mil TSOP II

packages

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Lead-free product listed for each configuration

(RoHS compliant)