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LTC4355ISPBF Datasheet(PDF) 8 Page - Linear Technology |
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LTC4355ISPBF Datasheet(HTML) 8 Page - Linear Technology |
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8 / 20 page  LTC4355 8 4355fe APPLICATIONS INFORMATION MOSFET Selection The LTC4355 drives N-channel MOSFETs to conduct the load current. The important features of the MOSFETs are on-resistance RDS(ON),themaximumdrain-sourcevoltage VDSS, and the threshold voltage. The gate drive for the MOSFET is guaranteed to be greater than 4.5V when the supply voltage at VOUT is between 9V and 20V. When the supply voltage at VOUT is greater than 20V, the gate drive is guaranteed to be greater than 10V. The gate drive is limited to less than 18V. This allows the use of logic level threshold N-channel MOSFETs and standard N-channel MOSFETs above 20V. An external Zener diode can be used to clamp the potential from the MOSFET’s gate to source if the rated breakdown voltage is less than 18V. See the Typical Applications section for an example. The maximum allowable drain-source voltage, BVDSS, must be higher than the supply voltages. If an input is connected to GND, the full supply voltage will appear across the MOSFET. If the voltage drop across either MOSFET exceeds the con- figurable ΔVSD(FLT)faultthreshold,the VDSFLTpinandthe PWRFLT pin corresponding to the faulting channel pull low. TheRDS(ON)shouldbesmallenoughtoconductthemaximum load current while not triggering a fault, and to stay within the MOSFET’s power rating at the maximum load current (I2 • RDS(ON)). Fault Conditions The LTC4355 monitors fault conditions and shunts current away from LEDs or opto-couplers, turning each one off to indicate a specific fault condition (see Table 1). When the voltage drop across the pass transistor is higher than the configurable ΔVSD(FLT) fault threshold, the internal pull-down at the VDSFLT pin and the PWRFLT1 or PWRFLT2 pin corresponding to the faulting channel turns on. The ΔVSD(FLT) threshold is configured by the SET pin. Tying SET to GND, tying SET to a 100k resistor connected to GND, or floating SET configures ΔVSD(FLT) to 250mV, 500mV, or 1.5V respectively. Table 1. Fault Table ΔVSD1 < ΔVSD(FLT) VIN1 > 3.5V VMON1 > 1.23V VDSFLT* FUSEFLT1 PWRFLT1 True True True Hi-Z Hi-Z Hi-Z True True False Hi-Z Hi-Z Pull-Down True False True Hi-Z Pull-Down Hi-Z True False False Hi-Z Pull-Down Pull-Down False True True Pull-Down Hi-Z Pull-Down False True False Pull-Down Hi-Z Pull-Down False False True Pull-Down Pull-Down Pull-Down False False False Pull-Down Pull-Down Pull-Down * ΔVSD2 < ΔVSD(FLT) Fault conditions that may cause a high voltage across the pass transistor include: a MOSFET open on the higher supply, excessive MOSFET current due to overcurrent on the load or a shorted MOSFET on the lower supply. During startup or when a switchover between supplies occurs, the VDSFLT pin and PWRFLT1 or PWRFLT2 pin may momentarily indicate that the forward voltage has exceeded the programmed threshold during the short interval when the MOSFET gate ramps up and the body diode conducts. The PWRFLT pins are additionally used to indicate if either input supply is below its normal regulation range. If the voltage at the MON1 or MON2 pin is less than VMON(TH), typically 1.23V, the corresponding PWRFLT1 or PWRFLT2 pin will pull low. A resistive divider connected to the input supply drives the MON pin for the corresponding supply, configuring the PWRFLT threshold for that supply. Be sure to account for the tolerance of the MON pin threshold, the resistor tolerances, and the regulation range of the supply being monitored. Also, ensure that the voltage on the MON pin will not exceed 7V. The FUSEFLT pins are used to indicate the status of the input fuses. If one of the IN pins falls below VINx(TH), typi- cally 3.5V, the FUSEFLT pin corresponding to that supply will pull low. The IN pins each sink a minimum of 0.5mA, enough to pull the pin low after an input fuse blows open. If there is a possibility that the MOSFET leakage current can be greater than 0.5mA, a resistor can be connected between the IN pin and GND to sink more current. Note that if the input supply voltage is less than VINx(TH) the FUSEFLT pin will pull low. |
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