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LTC3860EUHPBF Datasheet(PDF) 10 Page - Linear Technology |
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LTC3860EUHPBF Datasheet(HTML) 10 Page - Linear Technology |
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10 / 36 page  LTC3860 0 3860f operaTion (Refer to Functional Diagram) Main Control Architecture The LTC3860 is a dual-channel/dual-phase, constant frequency, voltage mode controller for DC/DC step-down applications. It is designed to be used in a synchronous switching architecture with external integrated-driver MOSFETs or external drivers and N-channel MOSFETs using single wire three-state PWM interfaces. The control- ler allows the use of sense resistors or lossless inductor DCR current sensing to maintain current balance between phasesandtoprovideovercurrentprotection.Theoperating frequencyisselectablefrom250kHzto1.25MHz.Tomulit- plytheeffectiveswitchingfrequency,multiphaseoperation can be extended to 3, 4, 6, or 12 phases by paralleling up to 6 controllers. In single or 3-phase operation, the 2nd or 4th channel can be used as an independent output. The output of the differential amplifier is connected to the error amplifier inverting input (FB) through a resistor divider. The remote sense differential amplifier output (VSNSOUT)providesasignalequaltothedifferentialvoltage (VSNSP – VSNSN) sensed across the output capacitor, but re-referenced to the local ground (SGND). This permits accurate voltage sensing at the load, without regard to the potential difference between its ground and local ground. In the main voltage mode control loop, the error ampli- fier output (COMP) directly controls the converter duty cycle in order to drive the FB pin to 0.6V in steady state. Dynamic changes in output load current can perturb the output voltage. When the output is below regulation, COMP rises, increasing the duty cycle. If the output rises above regulation, COMP will decrease, decreasing the duty cycle. As the output approaches regulation, COMP will settle to the steady-state value representing the step- down conversion ratio. Innormaloperation,thePWMlatchissethighatthebegin- ning of the clock cycle (assuming COMP > 0.5V). When the (line feedforward compensated) PWM ramp exceeds the COMP voltage, the comparator trips and resets the PWM latch. If COMP is less than 0.5V at the beginning of the clock cycle, as in the case of an overvoltage at the outputs, the PWM pin remains low throughout the entire cycle. When the PWM pin goes high it has a minimum on-time of approximately 20ns and a minimum off-time of approximately 1/12th the switching period. Current Sharing Inmultiphaseoperation,theLTC3860alsoincorporatesan auxiliarycurrentsharingloop.Inductorcurrentissampled each cycle. Each phase’s current sense amplifier output is averaged at the IAVGpin.Asmallcapacitorconnectedfrom IAVGtoGND(typically100pF)storesavoltagecorrespond- ing to the instantaneous average current of all phases. Each phase integrates the difference between its current and the average. Within each phase the integrator output is proportionally summed with the system error amplifier voltage(COMP),adjustingthatphase’sdutycycletoequal- izethecurrents. WhenmultipleICsaredaisy-chainedthe IAVG pins must be connected together. When the phases are operated independently, the IAVG pin should be tied to ground. Figure 1 shows a transient load step with 50% inductor mismatch in a 2-phase system. Figure 1 VOUT(AC) 100mV/DIV 50µs/DIV 3860 G05 VIN = 12V VOUT = 1.2V ILOAD = 0A TO 25A IL1 = 320nH 10A/DIV ILOAD 20A/DIV IL2 = 220nH 10A/DIV |
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