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STM32F100R6H6B Datasheet(PDF) 29 Page - STMicroelectronics |
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STM32F100R6H6B Datasheet(HTML) 29 Page - STMicroelectronics |
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29 / 84 page  STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Pinouts and pin description Doc ID 16455 Rev 2 29/84 90 56 A4 40 PB4 I/O FT NJTRST PB4 / TIM3_CH1 SPI1_MISO 91 57 C4 41 PB5 I/O PB5 I2C1_SMBA / TIM16_BKIN TIM3_CH2 / SPI1_MOSI 92 58 D3 42 PB6 I/O FT PB6 I2C1_SCL(12)/ TIM4_CH1(10)(12) TIM16_CH1N USART1_TX 93 59 C3 43 PB7 I/O FT PB7 I2C1_SDA(12)/ TIM17_CH1N TIM4_CH2(10)(12) USART1_RX 94 60 B4 44 BOOT0 I BOOT0 95 61 B3 45 PB8 I/O FT PB8 TIM4_CH3(10)(12) / TIM16_CH1(12) / CEC(12) I2C1_SCL 96 62 A3 46 PB9 I/O FT PB9 TIM4_CH4(10)(12) / TIM17_CH1(12) I2C1_SDA 97 - - - PE0 I/O FT PE0 TIM4_ETR(10) 98 - - - PE1 I/O FT PE1 99 63 D4 47 VSS_3 SVSS_3 100 64 E4 48 VDD_3 SVDD_3 1. I = input, O = output, S = supply, HiZ= high impedance. 2. FT= 5 V tolerant. 3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 11. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch and since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is restricted: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead. 8. I2C2 is not present on low-density value line devices. 9. SPI2 is not present on low-density value line devices. 10. TIM4 is not present on low-density value line devices. 11. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages and C1 and C2 in the TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. 12. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. Table 4. STM32F100xx pin definitions (continued) Pins Pin name Main function(3) (after reset) Alternate functions(3)(4) Default Remap |
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