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AM1808AZWTD3 Datasheet(PDF) 1 Page - Texas Instruments |
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AM1808AZWTD3 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 264 page AM1808 www.ti.com SPRS653 – FEBRUARY 2010 AM1808 ARM Microprocessor Check for Samples: AM1808 1 AM1808 ARM Microprocessor 1.1 Features 12 Interfaces • 375/456-MHz ARM926EJ-S™ RISC MPU • Two Master/Slave Inter-Integrated Circuit (I2C • ARM926EJ-S Core Bus™) – 32-Bit and 16-Bit (Thumb®) Instructions • One Host-Port Interface (HPI) With 16-Bit-Wide – Single Cycle MAC Muxed Address/Data Bus For High Bandwidth – ARM® Jazelle® Technology • Programmable Real-Time Unit Subsystem – EmbeddedICE-RT™ for Real-Time Debug (PRUSS) • ARM9 Memory Architecture – Two Independent Programmable Realtime – 16K-Byte Instruction Cache Unit (PRU) Cores – 16K-Byte Data Cache • 32-Bit Load/Store RISC architecture – 8K-Byte RAM (Vector Table) • 4K Byte instruction RAM per core – 64K-Byte ROM • 512 Bytes data RAM per core • Enhanced Direct-Memory-Access Controller 3 • PRU Subsystem (PRUSS) can be disabled (EDMA3): via software to save power – 2 Channel Controllers • Register 30 of each PRU is exported from – 3 Transfer Controllers the subsystem in addition to the normal – 64 Independent DMA Channels R31 output of the PRU cores. – 16 Quick DMA Channels – Standard power management mechanism – Programmable Transfer Burst Size • Clock gating • 128K-Byte On-chip Memory • Entire subsystem under a single PSC clock gating domain • 1.8V or 3.3V LVCMOS IOs (except for USB and DDR2 interfaces) – Dedicated interrupt controller • Two External Memory Interfaces: – Dedicated switched central resource – EMIFA • USB 1.1 OHCI (Host) With Integrated PHY (USB1) • NOR (8-/16-Bit-Wide Data) • USB 2.0 OTG Port With Integrated PHY (USB0) • NAND (8-/16-Bit-Wide Data) – USB 2.0 High-/Full-Speed Client • 16-Bit SDRAM With 128 MB Address Space – USB 2.0 High-/Full-/Low-Speed Host – DDR2/Mobile DDR Memory Controller – End Point 0 (Control) • 16-Bit DDR2 SDRAM With 512 MB – End Points 1,2,3,4 (Control, Bulk, Interrupt or Address Space or ISOC) Rx and Tx • 16-Bit mDDR SDRAM With 256 MB • One Multichannel Audio Serial Port: Address Space – Transmit/Receive Clocks • Three Configurable 16550 type UART Modules: – Two Clock Zones and 16 Serial Data Pins – With Modem Control Signals – Supports TDM, I2S, and Similar Formats – 16-byte FIFO – DIT-Capable – 16x or 13x Oversampling Option – FIFO buffers for Transmit and Receive • LCD Controller • Two Multichannel Buffered Serial Ports: • Two Serial Peripheral Interfaces (SPI) Each – Transmit/Receive Clocks With Multiple Chip-Selects – Two Clock Zones and 16 Serial Data Pins • Two Multimedia Card (MMC)/Secure Digital (SD) – Supports TDM, I2S, and Similar Formats Card Interface with Secure Data I/O (SDIO) – AC97 Audio Codec Interface 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 ARM926EJ-S is a trademark of ARM Limited. ADVANCE INFORMATION concerns new products in the sampling Copyright © 2010, Texas Instruments Incorporated or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. |
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