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UCD9224RGZR Datasheet(PDF) 3 Page - Texas Instruments |
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UCD9224RGZR Datasheet(HTML) 3 Page - Texas Instruments |
3 / 34 page UCD9224 www.ti.com SLVSA35 – JANUARY 2010 ELECTRICAL CHARACTERISTICS (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ERROR AMPLIFIER INPUTS EAPn, EANn VCM Common mode voltage each pin –0.15 1.848 V VERROR Internal error voltage range AFE_GAIN field of CLA_GAINS = 0(1) –256 248 mV EAP-EAN Error voltage digital resolution AFE_GAIN field of CLA_GAINS = 3 1 mV REA Input Impedance Ground reference 0.5 1.5 3 M Ω IOFFSET Input offset current 1 k Ω source impedence –5 5 µA Vref 10-bit DAC Vref Reference voltage setpoint 0 1.6 V Vrefres Reference voltage resolution 1.56 mV ANALOG INPUTS CS-1A, CS-1B, CS-2A, CS-3A, Vin/Iin, Temperature, ADDR-0, ADDR-1, Vtrack, ADCref VADDR_OPEN Voltage indicating open pin ADDR-0, ADDR-1 open 2.37 V VADDR_SHORT Voltage indicating shorted pin ADDR-0, ADDR-1 short to ground 0.36 V Inputs: Vin/Iin, Vtrack, Vtemperature CS-1A, VADC_RANGE Measurement range for voltage monitoring 0 2.5 V CS-1B, CS-2A, CS-3A Over-current comparator threshold voltage VOC_THRS Inputs: CS-1A, CS-1B, CS-2A, CS-3A 0.032 2 V range(2) Over-current comparator threshold voltage VOC_RES Inputs: CS-1A, CS-1B, CS-2A, CS-3A 31.25 mV range ADCref External reference input 1.8 V33A V Tempinternal Int. temperature sense accuracy Over range from 0°C to 125°C –5 5 °C INL ADC integral nonlinearity –2.5 2.5 mV Ilkg Input leakage current 3V applied to pin 100 nA RIN Input impedance Ground reference 8 M Ω CIN Current Sense Input capacitance 10 pF DIGITAL INPUTS/OUTPUTS DGND1 VOL Low-level output voltage IOL = 6 mA (3), V 33D = 3 V V +0.25 V33D VOH High-level output voltage IOH = -6 mA (4), V 33D = 3 V V –0.6V VIH High-level input voltage V33D = 3V 2.1 3.6 V VIL Low-level input voltage V33D = 3.5 V 1.4 V SYSTEM PERFORMANCE VRESET Voltage where device comes out of reset V33D Pin 2.3 2.4 V tRESET Pulse width needed for reset nRESET pin 2 µs Vref commanded to be 1V at 25°C, VRefAcc Setpoint reference accuracy –10 10 mV AFEgain = 4, 1V input to EAP/N measured at output of the EADC(5) Setpoint reference accuracy over temperature –40°C to 125°C –20 20 mV VDiffOffset Differential offset between gain settings AFEgain = 4 compared to AFEgain = 1, 2, or 8 –4 4 mV 240 + 1 tDelay Digital compensator delay 240 switching ns cycle FSW Switching frequency 15.260 2000 kHz Duty Max and Min duty cycle 0% 100% V33 slew rate between 2.3V and 2.9V, V33Slew Minimum V33 slew rate during power on 0.25 V/ms V33A = V33D tretention Retention of configuration parameters TJ = 25°C 100 Years Write_Cycles Number of nonvolatile erase/write cycles TJ = 25°C 20 K cycles (1) See the UCD92xx PMBus Command Reference for the description of the AFE_GAIN field of CLA_GAINS command. (2) Can be disabled by setting to '0'0 (3) The maximum IOL, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. (4) The maximum IOH, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified. (5) With default device calibration. PMBus calibration can be used to improve the regulation tolerance Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3 |
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