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STM32F100RBT6BTR Datasheet(PDF) 20 Page - STMicroelectronics |
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STM32F100RBT6BTR Datasheet(HTML) 20 Page - STMicroelectronics |
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20 / 84 page  Description STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 20/84 Doc ID 16455 Rev 2 2.16.6 SysTick timer This timer is dedicated for OS, but could also be used as a standard down counter. It features: ● A 24-bit down counter ● Autoreload capability ● Maskable system interrupt generation when the counter reaches 0. ● Programmable clock source 2.17 I²C bus The I²C bus interface can operate in multimaster and slave modes. It can support standard and fast modes. It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. The interface can be served by DMA and it supports SM Bus 2.0/PM Bus. 2.18 Universal synchronous/asynchronous receiver transmitter (USART) The STM32F100xx value line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3). The available USART interfaces communicate at up to 3 Mbit/s. They provide hardware management of the CTS and RTS signals, they support IrDA SIR ENDEC, the multiprocessor communication mode, the single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller. 2.19 Serial peripheral interface (SPI) Up to two SPIs are able to communicate up to 12 Mbit/s in slave and master modes in full- duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. Both SPIs can be served by the DMA controller. 2.20 HDMI (high-definition multimedia interface) consumer electronics control (CEC) The STM32F100xx value line embeds a HDMI-CEC controller that provides hardware support of consumer electronics control (CEC) (Appendix supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. |
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