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AD5174 Datasheet(PDF) 15 Page - Analog Devices

Part No. AD5174
Description  Single-Channel, 1024-Position, Digital Rheostat with SPI Interface and 50-TP Memory
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD5174 Datasheet(HTML) 15 Page - Analog Devices

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AD5174
Rev. 0 | Page 15 of 20
Table 10. Memory Map
Command Number
Data Byte[DB9:DB0]1
Register Contents
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
5
X
X
X
0
0
0
0
0
0
0
Reserved
X
X
X
0
0
0
0
0
0
1
1st programmed wiper location (0x01)
X
X
X
0
0
0
0
0
1
0
2nd programmed wiper location (0x02)
X
X
X
0
0
0
0
0
1
1
3rd programmed wiper location (0x03)
X
X
X
0
0
0
0
1
0
0
4th programmed wiper location (0x04)
X
X
X
0
0
0
1
0
1
0
10th programmed wiper location (0xA)
X
X
X
0
0
1
0
1
0
0
20th programmed wiper location (0x14)
X
X
X
0
0
1
1
1
1
0
30th programmed wiper location (0x1E)
X
X
X
0
1
0
1
0
0
0
40th programmed wiper location (0x28)
X
X
X
0
1
1
0
0
1
0
50th programmed wiper location (0x32)
X
X
X
0
1
1
1
0
0
1
MSB resistance tolerance (0x39)
X
X
X
0
1
1
1
0
1
0
LSB resistance tolerance (0x3A)
1 X is don’t care.
DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes: it can be
used to read the contents of the wiper setting and 50-TP values
using Command 2 and Command 5, respectively (see Table 6),
or the SDO pin can be used in daisy-chain mode. The remaining
instructions are valid for daisy chaining multiple devices in
simultaneous operations. Data is clocked out of SDO on the
rising edge of SCLK. Daisy chaining minimizes the number
of port pins required from the controlling IC. The SDO pin
contains an open-drain N-channel FET that requires a pull-up
resistor if this pin is used. As shown in Figure 26, users need
to tie the SDO pin of one package to the DIN pin of the next
package. Users may need to increase the clock period, because
the pull-up resistor and the capacitive loading at the SDO-to-
DIN interface may require additional time delay between
subsequent devices. When two AD5174 devices are daisy-
chained, 32 bits of data are required. The first 16 bits go
to U2, and the second 16 bits go to U1. Keep the SYNC pin
low until all 32 bits are clocked into their respective serial
registers. The SYNC pin is then pulled high to complete the
operation.
DIN
MOSI
SS
SCLK
SDO
SCLK
DIN
SDO
AD5174
U1
AD5174
U2
SYNC
SCLK
SYNC
VDD
µC
RP
2.2kΩ
Figure 26. Daisy-Chain Configuration Using SDO
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5174 employs a three-stage
segmentation approach as shown in Figure 27. The AD5174
wiper switch is designed with the transmission gate CMOS
topology.
A
W
10-BIT
ADDRESS
DECODER
RL
RL
RM
RM
RW
SW
RW
Figure 27. Simplified RDAC Circuit


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