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DM9161AEP Datasheet(PDF) 37 Page - Davicom Semiconductor, Inc. |
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DM9161AEP Datasheet(HTML) 37 Page - Davicom Semiconductor, Inc. |
37 / 45 page DM9161A 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 37 Final Version: DM9161A-DS-F01 October 16, 2009 9.4.3 MDC/MDIO Timing Symbol Parameter Min. Typ. Max. Unit Conditions t0 MDC Cycle Time 80 - - ns t1 MDIO Setup Before MDC 10 - - ns When OUTPUT By STA t2 MDIO Hold After MDC 10 - - ns When OUTPUT By STA t3 MDC To MDIO Output Delay 0 - 300 ns When OUTPUT By DM9161A 9.4.4 MDIO Timing When OUTPUT by STA MDC t1 MDIO 10ns (Min) t2 10ns (Min) t0 9.4.5 MDIO Timing When OUTPUT by DM9161A MDC t3 MDIO 0 - 300 ns t0 |
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