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DM9103EP Datasheet(PDF) 25 Page - Davicom Semiconductor, Inc.

Part # DM9103EP
Description  10/100 Mbps 3-port Ethernet Switch Controller with PCI Interface
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Manufacturer  DAVICOM [Davicom Semiconductor, Inc.]
Direct Link  http://www.davicom.com.tw
Logo DAVICOM - Davicom Semiconductor, Inc.

DM9103EP Datasheet(HTML) 25 Page - Davicom Semiconductor, Inc.

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DM9103
3-port switch with PCI Interface
Preliminary datasheet
25
DM9103-DS-P02
September 26, 2007
6.2.1 System Control Register (CR0)
Bit
Name
Default
Description
31:24
Reserved
DEH,RO
Reserved
25:22
Reserved
00,RO
Reserved
21
MRM
0,RW
Memory Read Multiple
When set, the DM9103 will use memory read multiple command (C/BE3~0 1100)
when it initialize the memory read burst transaction as a master device
When reset, it will use memory read command (C/BE3 ~ 0 = 0110) for the same
master operation
20
Reserved
0,RW
Reserved
19:1
Reserved
0,RO
Reserved
0
SR
0,RW
Software Reset
When set, the DM9103 will make a internal reset cycle. All consequent action to
DM9103 should wait at least 32 PCI clock cycles for its self-cleared.
6.2.2 Transmit Descriptor Poll Demand (CR1)
Bit
Name
Default
Description
31:0
TDP
FFFFFFFFH
,WO
Transmit Descriptor Polling Command
Writing any value to this port will force DM9103 to poll the transmit descriptor. If
the acting descriptor is not available, transmit process will return to suspend state.
If the descriptor shows buffer available, transmit process will begin the data
transfer.
6.2.3 Receive Descriptor Poll Demand (CR2)
Bit
Name
Default
Description
31:0
RDP
FFFFFFFFH
,WO
Receive Descriptor Polling Command
Writing any value to this port will force DM9103 to poll the receive descriptor. If the
acting descriptor is not available, receive process will return to suspend state.
If the descriptor shows buffer available, receive process will begin the data transfer.
6.2.4 Receive Descriptor Base Address (CR3)
Bit
Name
Default
Description
31:0
RDBA
00000000H,
RW
Receive Descriptor Base Address
This register defines base address of receive descriptor-chain. The receive
descriptor- polling command, after CR3 is set, will make DM9103 to fetch the
descriptor at the Base-Address.
This is a working register, so the value of reading is unpredictable.


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