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DM9102HEP Datasheet(PDF) 35 Page - Davicom Semiconductor, Inc. |
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DM9102HEP Datasheet(HTML) 35 Page - Davicom Semiconductor, Inc. |
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35 / 77 page  DM9102H Single Chip Fast Ethernet NIC Controller Final Version: DM9102H-12-DS-F01 February 15, 2008 30 7 RXPCS 0,RO The decode of the pause packet. 6 VLAN 0,RW VLAN length Capability Enable It is set to enable the VLAN length mode. 5 TWDR 0,RW Time Interval of Watchdog Release This bit is used to select the time interval between receive Watchdog timer expiration until re-enabling of the receive channel. When this bit is set, the time interval is 40~48-bit time. When this bit is reset, it is 16~24 bits time. 4 TWDE 0,RW Watchdog Timer Disable When set, the Watchdog Timer is disabled. Otherwise it is enabled. 3:1 Reserved 0,RO Reserved 0 TJE 0,RW Transmit Jabber Disable When set, the transmit Jabber is disabled. Otherwise it is enabled. 6.3 PHY Management Register Set Offset Register Name Description Default value after reset 0 BMCR Basic Mode Control Register 3100H 1 BMSR Basic Mode Status Register 7849H 2 PHYIDR1 PHY Identifier Register #1 0181H 3 PHYIDR2 PHY Identifier Register #2 B8B0H 4 ANAR Auto-Negotiation Advertisement Register 01E1H 5 ANLPAR Auto-Negotiation Link Partner Ability Register 0000H 6 ANER Auto-Negotiation Expansion Register 0000H 7-15 Reserved Reserved 0000H 10H DSCR DAVICOM Specified Configuration Register 0414H 11H DSCSR DAVICOM Specified Configuration/Status Register F210H 12H 10BTCSR 10BASE-T Configuration/Status Register 7800H Others Reserved Reserved for future use, do not read/write to these Registers 0000H Key to Default In the register description that follows, the default column takes the form: <Reset Value>, <Access Type> / <Attribute(s)> Where： <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value (PIN#) Value latched in from pin # at reset <Access Type>: RO = Read only RW = Read/Write <Attribute (s)>: SC = Self clearing P = Value permanently set LL = Latching low LH = Latching high |
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