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DM9102DEP Datasheet(PDF) 34 Page - Davicom Semiconductor, Inc. |
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DM9102DEP Datasheet(HTML) 34 Page - Davicom Semiconductor, Inc. |
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34 / 70 page  34 Final Version: DM9102D-DS-F01 May 10, 2006 Bit Name Default Description 15 100BASE-T4 0,RO/P 100BASE-T4 Capable: 1=DM9102D is able to perform in 100BASE-T4 mode. 0=DM9102D is not able to perform in 100BASE-T4 mode. 14 100BASE-TX Full Duplex 1,RO/P 100BASE-TX FULL DUPLEX CAPABLE: 1= DM9102D is able to perform 100BASE-TX in Full Duplex mode. 0= DM9102D is not able to perform 100BASE-TX in Full Duplex mode. 13 100BASE-TX Half Duplex 1,RO/P 100BASE-TX Half Duplex Capable: 1=DM9102D is able to perform 100BASE-TX in Half Duplex mode. 0=DM9102D is not able to perform 100BASE-TX in Half Duplex mode. 12 10BASE-T Full Duplex 1,RO/P 10BASE-T Full Duplex Capable: 1=DM9102D is able to perform 10BASE-T in Full Duplex mode. 0=DM9102D is not able to perform 10BASE-T in Full Duplex mode. 11 10BASE-T Half Duplex 1,RO/P 10BASE-T Half Duplex Capable: 1=DM9102D is able to perform 10BASE-T in Half Duplex mode. 0=DM9102D is not able to perform 10BASE-T in Half Duplex mode . 10:7 Reserved 0000,RO Reserved: Write as 0, ignore on read 6 MF Preamble Suppression 1,RW MII Frame Preamble Suppression: 1=PHY will accept management frames with preamble suppressed. 0=PHY will not accept management frames with preamble suppressed. 5 Auto-negotiation Complete 0,RO Auto-negotiation Complete: 1=Auto-negotiation process is completed. 0=Auto-negotiation process is not completed. 4 Remote Fault 0,RC/LH Remote Fault: 1= Remote fault condition detected (cleared on read or by a chip reset). Fault criteria and detection method is DM9102D specific implementation. This bit will set after the RF bit in the ANLPAR (bit 13, register address 05) is set 0= No remote fault condition detected 3 Auto-negotiation Ability 1,RO/P Auto Configuration Ability: 1=DM9102D is able to perform Auto-negotiation 0=DM9102D is not able to perform Auto-negotiation 2 Link Status 0,RC/LL Link Status: 1=Valid link established (for either 10Mbps or 100Mbps operation) 0=Link not established The link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the Link Status bit to be cleared and remain cleared until it is read via the management interface 1 Jabber Detect 0,RC/LH Jabber Detect: 1=Jabber condition detected 0=No jabber This bit is implemented with a latching function. Jabber conditions will set this bit unless it is cleared by a read to this register through a management interface or a DM9102D reset. This bit works only in 10Mbps mode 0 Extended Capability 1,RO/P Extended Capability: 1=Extended register capability 0=Basic register capability only 6.3.3 PHY Identifier Register #1 (PHYIDR1) – 2 |
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