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DM9000BEP Datasheet(PDF) 36 Page - Davicom Semiconductor, Inc. |
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DM9000BEP Datasheet(HTML) 36 Page - Davicom Semiconductor, Inc. |
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36 / 56 page  DM9000B Ethernet Controller with General Processor Interface Final 36 Version: DM9000B-13-DS-F02 June 4, 2009 8.11 Power down Control Register (PWDOR) - 19 Bit Bit Name Default Description 19.15 -19.9 Reserved 0, RO Reserved Read as 0, ignore on write 19.8 PD10DRV 0, RW Vendor power down control test 19.7 PD100DL 0, RW Vendor power down control test 19.6 PDchip 0, RW Vendor power down control test 19.5 PDcom 0, RW Vendor power down control test 19.4 PDaeq 0, RW Vendor power down control test 19.3 PDdrv 0, RW Vendor power down control test 19.2 PDedi 0, RW Vendor power down control test 19.1 PDedo 0, RW Vendor power down control test 19.0 PD10 0, RW Vendor power down control test * When selected, the power down value is control by Register 20.0 8.12 (Specified config) Register – 20 Bit Bit Name Default Description 20.15 TSTSE1 0,RW Vendor test select control 20.14 TSTSE2 0,RW Vendor test select control 20.13 FORCE_TXSD 0,RW Force Signal Detect 1: force SD signal OK in 100M 0: normal SD signal. 20.12 FORCE_FEF 0,RW Vendor test select control 20.11 PREAMBLEX 0,RW Preamble Saving Control 0: when bit 10 is set, the 10BASE-T transmit preamble count is reduced. When bit 11 of register 1DH is set, 12-bit preamble is reduced; otherwise 22-bit preamble is reduced. 1: transmit preamble bit count is normal in 10BASE-T mode 20.10 TX10M_PWR 0,RW 10BASE-T mode Transmit Power Saving Control 1: enable transmit power saving in 10BASE-T mode 0: disable transmit power saving in 10BASE-T mode 20.9 NWAY_PWR 0,RW Auto-negotiation Power Saving Control 1: disable power saving during auto-negotiation period 0: enable power saving during auto-negotiation period 20.8 Reserved 0, RO Reserved Read as 0, ignore on write 20.7 MDIX_CNTL MDI/MDIX,RO The polarity of MDI/MDIX value 1: MDIX mode 0: MDI mode 20.6 AutoNeg_lpbk 0,RW Auto-negotiation Loop-back 1: test internal digital auto-negotiation Loop-back 0: normal. 20.5 Mdix_fix Value 0, RW MDIX_CNTL force value: When Mdix_down = 1, MDIX_CNTL value depend on the register value. |
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