8 ______________________________________________________________________________________

Power-Line Communications (PLC) Integrated

Analog Front-End Transceiver

Pin Configuration

Pin Description

REF

GND5

ENTX

ENRX

GSUB

RXCLK

TXCLK

RXDATA

TXDATA

RXCONV

TXCONV

GND1

RXINP

RXINN

I.C.

I.C.

I.C.

I.C.

TXOUTP

TXOUTN

GND2

LQFP

+

MAX2991

36

35

34

33

32

31

30

29

28

27

26

25

1

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

2

3

4

5

6

7

8

9

10

11

12

PIN

NAME

FUNCTION

1

Analog Power-Supply 1. Bypass to GND1 with 100nF and 10FF capacitors in parallel located close to

2

GND1

Analog Ground 1. Connect GND1 to the PCB ground.

3

RXINP

AC Power-Line Positive Input

4

RXINN

AC Power-Line Negative Input

5, 6, 48

I.C.

Internal Connection. Connect to the PCB ground.

7, 8

I.C.

Internal Connection. Leave unconnected.

9

TXOUTP

AC Power-Line Positive Output

10

TXOUTN

AC Power-Line Negative Output

11

GND2

Analog Ground 2. Connect GND2 to the PCB ground.

12

Analog Power-Supply 2. Bypass to GND2 with 100nF and 10FF capacitors in parallel located close to

13

AGCFRZ

Active-High AGC Freeze-Mode Enable. Drive AGCFRZ high to place the AGC adaptation in freeze

mode. Drive AGCFRZ low to allow continuous AGC adaptation.