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AS3524 Datasheet(PDF) 57 Page - ams AG |
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AS3524 Datasheet(HTML) 57 Page - ams AG |
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57 / 124 page  AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 57 - 124 Table 36 I2SOUT control register Name Base Default I2SOUT_CONTROL AS3525_I2SOUT_BASE 0x0C Control register Offset: 0x0000 7 bit wide read/write register containing the control bits of the I2SOUTIF. Bit Bit Name Default Access Bit Description 6 DMA_req_en 0 R/W DMA request enable 0: disable 1: enable 5 sdata_lb 0 R/W I2SDATA loopback from I2SINIF 0: I2SOUT_SDATA source is I2SOUTIF’s FIFO 1: I2SOUT_SDATA source is loopback value from I2SINIF (signal I2SIN_FDATA) 4 mclk_invert 0 R/W Invert MCLK 0: disable (SCLK changes at MCLK’s falling edge) 1: enable (SCLK changes at MCLK’s rising edge) 3 stereo_mode 1 R/W Audio samples provided by processor 0: mono 1: stereo 2 18bit_mode 1 R/W Bit width of audio samples provided by processor 0: 16 bit 1: 18 bit 1,0 osr 00 R/W Oversampling rate 00: 128x 01: 256x 10: 512x 11: 128x CAUTION: The control bit sdata_lb can only be set, if the I2SIN_FSDATA is synchronous to I2SOUT_SCLK. This is the case if AFE is used together with the AS3525 (in this case the I2SINIF uses also I2SOUT_CLK). Table 37 I2S Output mask register Name Base Default I2SOUT_MASK AS3525_I2SOUT_BASE 0x00 Interrupt mask register Offset: 0x0004 The interrupt mask register determines which status flags generate an interrupt by setting the corresponding bit to 1. Bit Bit Name Default Access Bit Description 7 reserved 0 R/W stereo18_status cannot assert interrupt request 6 I2SOUT_MASK_POER 0 R/W 1 enables the FIFO POP error interrupt 5 I2SOUT_MASK_PUE 0 R/W 1 enables the FIFO PUSH is empty interrupt 4 I2SOUT_MASK_PUAE 0 R/W 1 enables the FIFO PUSH is almost empty interrupt 3 I2SOUT_MASK_PUHF 0 R/W 1 enables the FIFO PUSH is half full interrupt 2 I2SOUT_MASK_PUAF 0 R/W 1 enables the FIFO PUSH is almost full interrupt 1 I2SOUT_MASK_PUF 0 R/W 1 enables the FIFO PUSH is full interrupt 0 I2SOUT_MASK_PUER 0 R/W 1 enables the FIFO PUSH error interrupt |
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