T108 Release
Copyright by Terawins, Inc.
69
3.8.8
CCFL/LED Control Register
Address Offset:
E7h
Access:
Read/Write
Default Value:
80h
Size:
8 bits
Bit
Access
Symbol
Description
[7]
R/W
DIM_Source_Sel
DIM PWM source select:
0: analog PWM
1: digital PWM
[6]
R/W
DeadTimeControl
Dead Timer Control
[5:4]
R/W
OpnLmp_Current[1:0] Open Lamp Current setting
[3:0]
R/W
Inverter_Freq_Sel[1:0] Inverter frequency selection
3.8.9
PWM_1 General Control Register
Address Offset:
E8h
Access:
Read/Write
Default Value:
07h
Size:
8 bits
Bit
Access
Symbol
Description
[7:6]
R/W
PWM1_Low[4:3]
[5]
R/W
PWM1_Alt_Mode
1: Alternative PWM1 mode; 0: Legacy {PWM1_High/256} mode
[4]
R/W
PWM1_En
Enable PWM_1
[3]
RO
Reserved
[2:0]
R/W
PWM1_Freq_Sel
This register set the PWM1 counter base clock = XCLK / 2^N, N=0, 1,
2, 3, 5, 7, 9, 11. That is, the PWM1 freq = PWM1 base clock freq /
256.
3.8.10
PWM_1 Active High Time Counter Register
Address Offset:
E9h
Access:
Read/Write
Default Value:
80h
Size:
8 bits
Bit
Access
Symbol
Description
[7:5]
R/W
PWM1_High[7:5] /
PWM1_Low[2:0]
InPWM1 legacy mode, this register set PWM1 high time
(PWM1_High[7:0]/256) counted by PWM1 base clock.
In PWM1 Alternative mode, the PWM1 output: PWM1_High[4:0] /
( PWM1_Low[4:0] + PWM1_High[4:0]), based clock is divide from
XCLK , see P0_E8<2:0>
[4:0]
R/W
PWM1_High[4:0]
This register set PWM1 high time counted by PWM1 base clock. The
based clock is divide from XCLK , see P0_E8<2:0>
3.8.11
PWM_2 General Control Register
Address Offset:
EAh
Access:
Read/Write
Default Value:
27h
Size:
8 bits
Bit
Access
Symbol
Description
[7]
R/W
PWM2_Fine_Freq_Mode Select PWM_2 operating clock mode:
0: original XCLK/2^n mode, same as PWM1
1: fine frequency mode, XCLK/PWM2_Fine_Freq[10:0]
[6]
R/W
PWM2_Cfg_FineFreq Select which setting for programming
1: allow configuring clock divider: PWM2_Fine_Freq[10:0];
0: configure original PWM2_Freq_Sel[2:0] and PWM2_High[7:0]
[5]
R/W
CCFL_PWM_Sel
Select digital PWM output to CCFL:
0: PWM1 output
1: PWM2 output
[4]
R/W
PWM2_En
Enable PWM_2
[3]
RO
Reserved
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