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T108 Release
Copyright by Terawins, Inc.
57
3.4.18
Top Display Border Configuration LSB Register
Address Offset:
8Ch
Access:
Read/Write
Default Value:
00h
Size:
8 bits
Bit
Access
Symbol
Description
[7:0]
R/W
VTDSPLB[7:0]
3.4.19
Top Display Border Configuration MSB Register
Address Offset:
8Dh
Access:
Read/Write
Default Value:
00h
Size:
8 bits
Bit
Access
Symbol
Description
[7:6]
R/W
HDSPLB_GRID[1:0]
H grip precision,
00b: 1 pixel
01b: 4 pixels
10b: 16 pixels
11b: 32 pixels
[5:4]
R/W
VDSPLB_GRID[1:0]
V grip precision
00b: 1 line
01b: 4 lines
10b: 16 lines
11b: 32 lines
[3:2]
RO
Reserved
[1:0]
R/W
VTDSPLB[9:8]
3.4.20
Bottom Display Border Configuration LSB Register
Address Offset:
8Eh
Access:
Read/Write
Default Value:
00h
Size:
8 bits
Bit
Access
Symbol
Description
[7:0]
R/W
VBDSPLB[7:0]
3.4.21
Bottom Display Border Configuration MSB Register
Address Offset:
8Fh
Access:
Read/Write
Default Value:
00h
Size:
8 bits
Bit
Access
Symbol
Description
[7:2]
RO
Reserved
[1:0]
R/W
VBDSPLB[9:8]
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