LPC1343 datasheet(24/53 Pages) NXP

Part #	LPC1343

Description	32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and 8 kB SRAM; USB device

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Manufacturer	NXP [NXP Semiconductors]

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LPC1311_13_42_43_1

Product data sheet

Rev. 01 — 11 December 2009

24 of 53

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

7.17.5.1

Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.17.5.2

Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in addition analog blocks are shut

down for increased power savings. The user can conﬁgure the Deep-sleep mode to a

large extend, selecting any of the oscillators, any of the PLLs, the USB PHY (LPC134x

only), BOD, the ADC, and the ﬂash to be shut down or remain powered during Deep-sleep

mode. The user can also select which of the oscillators and analog blocks will be powered

up after the chip exits from Deep-sleep mode.

The GPIO pins (up to 40 pins total) serve as external wake-up pins to a dedicated start

logic to wake up the chip from Deep-sleep mode.

The timing of the wake-up process from Deep-sleep mode depends on which blocks are

selected to be powered down during deep-sleep.

For lowest power consumption, the clock source should be switched to IRC before

entering Deep-sleep mode, all oscillators and PLLs should be turned off during

deep-sleep, and the IRC should be selected as clock source when the chip wakes up from

deep-sleep. The IRC can be switched on and off glitch-free and provides a clean clock

signal after start-up.

If power consumption is not a concern, any of the oscillators and/or PLLs can be left

running in Deep-sleep mode to obtain short wake-up times when waking up from

deep-sleep.

7.17.5.3

Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the

WAKEUP pin. The LPC1311/13/42/43 can wake up from Deep power-down mode via the

WAKEUP pin.

7.18 System control

7.18.1 Reset

Reset has four sources on the LPC1311/13/42/43: the RESET pin, the Watchdog reset,

power-on reset (POR), and the Brown-Out Detection (BOD) circuit. The RESET pin is a

Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage

attains a usable level, starts the IRC and initializes the ﬂash controller.

When the internal reset is removed, the processor begins executing at address 0, which is

initially the reset vector mapped from the boot block. At that point, all of the processor and

peripheral registers have been initialized to predetermined values.

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LPC1343 Datasheet(PDF) 24 Page - NXP Semiconductors

LPC1343 Datasheet(HTML) 24 Page - NXP Semiconductors

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