CY8CLED08
Document Number: 001-12981 Rev. *E
Page 9 of 44
5. Pin Information
5.1 Pinouts
5.1.1 48-Pin Part Pinout SSOP
LEGEND: A = Analog, I = Input, and O = Output.
Table 5-1. 48-Pin Part Pinout (SSOP)
Pin
No.
Type
Pin
Name
Description
Figure 5-1. 48-Pin Device
Digital
Analog
1
I/O
I
P0[7]
Analog column mux input.
2
I/O
I/O
P0[5]
Analog column mux input and column output.
3
I/O
I/O
P0[3]
Analog column mux input and column output.
4
I/O
I
P0[1]
Analog column mux input.
5
I/O
P2[7]
6
I/O
P2[5]
7
I/O
I
P2[3]
Direct switched capacitor block input.
8
I/O
I
P2[1]
Direct switched capacitor block input.
9
I/O
P4[7]
10
I/O
P4[5]
11
I/O
P4[3]
12
I/O
P4[1]
13
Power
SMP
Switch Mode Pump (SMP) connection to external
components required.
14
I/O
P3[7]
15
I/O
P3[5]
16
I/O
P3[3]
17
I/O
P3[1]
18
I/O
P5[3]
19
I/O
P5[1]
20
I/O
P1[7]
I2C Serial Clock (SCL).
21
I/O
P1[5]
I2C Serial Data (SDA).
22
I/O
P1[3]
23
I/O
P1[1]
Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP SCLK[1].
24
Power
Vss
Ground connection.
25
I/O
P1[0]
Crystal Output (XTALout), I2C Serial Data (SDA),
ISSP SDATA[1].
26
I/O
P1[2]
27
I/O
P1[4]
Optional External Clock Input (EXTCLK).
Pin
No.
Digital
Analog
Pin
Name
Description
28
I/O
P1[6]
39
I/O
P4[6]
29
I/O
P5[0]
39
I/O
P4[6]
30
I/O
P5[2]
40
I/O
I
P2[0]
Direct switched capacitor block input.
31
I/O
P3[0]
41
I/O
I
P2[2]
Direct switched capacitor block input.
32
I/O
P3[2]
42
I/O
P2[4]
External Analog Ground (AGND).
33
I/O
P3[4]
43
I/O
P2[6]
External Voltage Reference (VRef).
34
I/O
P3[6]
44
I/O
I
P0[0]
Analog column mux input.
35
Input
XRES
Active high external reset with internal pull down. 45
I/O
I/O
P0[2]
Analog column mux input and column output.
36
I/O
P4[0]
46
I/O
I/O
P0[4]
Analog column mux input and column output.
37
I/O
P4[2]
47
I/O
I
P0[6]
Analog column mux input.
38
I/O
P4[4]
48
Power
Vdd
Supply voltage.
SSOP
A, I, P0[7]
Vdd
A, IO, P0[5]
P0[6], A, I
A, IO, P0[3]
P0[4], A, IO
A, I, P0[1]
P0[2], A, IO
P2[7]
P0[0], A, I
P2[5]
P2[6], External VRef
A, I, P2[3]
P2[4], External AGND
A, I, P2[1]
P2[2], A, I
P4[7]
P2[0], A, I
P4[5]
P4[6]
P4[3]
P4[4]
P4[1]
P4[2]
SMP
P4[0]
P3[7]
XRES
P3[5]
P3[6]
P3[3]
P3[4]
P3[1]
P3[2]
P5[3]
P3[0]
P5[1]
P5[2]
I2C SCL, P1[7]
P5[0]
I2C SDA, P1[5]
P1[6]
P1[3]
P1[4], EXTCLK
I2C SCL, XTALin, P1[1]
P1[2]
Vss
P1[0], XTALout, I2C SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
43
44
42
40
41
39
38
37
36
35
33
34
32
31
30
29
28
27
26
25
Note
1. These are the ISSP pins, which are not High Z at POR.
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