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CY8CLED08
Document Number: 001-12981 Rev. *E
Page 2 of 44
DIGITAL SYSTEM
SRAM
256 Bytes
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
Global Digital Interconnect
Global Analog Interconnect
PSoC
CORE
CPU Core (M8C)
SROM
Flash 16K
Digital
Block
Array
Multiply
Accum.
Switch
Mode
Pump
Internal
Voltage
Ref.
Digital
Clocks
POR and LVD
System Resets
Decimator
SYSTEM RESOURCES
ANALOG SYSTEM
Analog
Ref.
Analog
Input
Muxing
I C
2
Port 4
Port 3
Port 2
Port 1
Port 0
Analog
Drivers
System Bus
Analog
Block
Array
Port 5
Logic Block Diagram
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