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CY8C29666-24LFXI Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY8C29666-24LFXI
Description  PSoC짰 Programmable System-on-Chip?
Download  47 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C29666-24LFXI Datasheet(HTML) 10 Page - Cypress Semiconductor

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CY8C29466, CY8C29566
CY8C29666, CY8C29866
Document Number: 38-12013 Rev. *M
Page 10 of 47
9.2 44-Pin Part Pinout
Table 9-2. 44-Pin Part Pinout (TQFP)
Pin
No.
Type
Pin
Name
Description
Figure 9-2. CY8C29566 44-Pin PSoC Device
Digital
Analog
1
I/O
P2[5]
2
I/O
I
P2[3]
Direct switched capacitor block input.
3
I/O
I
P2[1]
Direct switched capacitor block input.
4
I/O
P4[7]
5
I/O
P4[5]
6
I/O
P4[3]
7
I/O
P4[1]
8
Power
SMP
Switch Mode Pump (SMP) connection to
external components required.
9
I/O
P3[7]
10
I/O
P3[5]
11
I/O
P3[3]
12
I/O
P3[1]
13
I/O
P1[7]
I2C Serial Clock (SCL).
14
I/O
P1[5]
I2C Serial Data (SDA).
15
I/O
P1[3]
16
I/O
P1[1]
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
17
Power
Vss
Ground connection.
18
I/O
P1[0]
Crystal (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
19
I/O
P1[2]
20
I/O
P1[4]
Optional External Clock Input (EXTCLK).
21
I/O
P1[6]
22
I/O
P3[0]
23
I/O
P3[2]
24
I/O
P3[4]
25
I/O
P3[6]
26
Input
XRES
Active high external reset with internal pull
down.
27
I/O
P4[0]
28
I/O
P4[2]
29
I/O
P4[4]
30
I/O
P4[6]
31
I/O
I
P2[0]
Direct switched capacitor block input.
32
I/O
I
P2[2]
Direct switched capacitor block input.
33
I/O
P2[4]
External Analog Ground (AGND).
34
I/O
P2[6]
External Voltage Reference (VREF).
35
I/O
I
P0[0]
Analog column mux input.
36
I/O
I/O
P0[2]
Analog column mux input and column output.
37
I/O
I/O
P0[4]
Analog column mux input and column output.
38
I/O
I
P0[6]
Analog column mux input.
39
Power
Vdd
Supply voltage.
40
I/O
I
P0[7]
Analog column mux input.
41
I/O
I/O
P0[5]
Analog column mux input and column output.
42
I/O
I/O
P0[3]
Analog column mux input and column output.
43
I/O
I
P0[1]
Analog column mux input.
44
I/O
P2[7]
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-ChipTechnical Reference Manual for details.
TQFP
P2[5]
P2[4],ExternalAGND
A, I, P2[3]
P2[2], A, I
A, I, P2[1]
P2[0], A, I
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
P4[1]
P4[0]
SMP
XRES
P3[7]
P3[6]
P3[5]
P3[4]
P3[3]
P3[2]
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
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