CY8C29466, CY8C29566
CY8C29666, CY8C29866
Document Number: 38-12013 Rev. *M
Page 9 of 47
9. Pinouts
The CY8C29x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, SMP, and XRES are not capable of Digital I/O.
9.1 28-Pin Part Pinout
Table 9-1. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
Pin
No.
Type
Pin
Name
Description
Figure 9-1. CY8C29466 28-Pin PSoC Device
Digital
Analog
1
I/O
I
P0[7]
Analog column mux input.
2
I/O
I/O
P0[5]
Analog column mux input and column output.
3
I/O
I/O
P0[3]
Analog column mux input and column output.
4
I/O
I
P0[1]
Analog column mux input.
5
I/O
P2[7]
6
I/O
P2[5]
7
I/O
I
P2[3]
Direct switched capacitor block input.
8
I/O
I
P2[1]
Direct switched capacitor block input.
9
Power
SMP
Switch Mode Pump (SMP) connection to
external components required.
10
I/O
P1[7]
I2C Serial Clock (SCL).
11
I/O
P1[5]
I2C Serial Data (SDA).
12
I/O
P1[3]
13
I/O
P1[1]
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
14
Power
Vss
Ground connection.
15
I/O
P1[0]
Crystal (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
16
I/O
P1[2]
17
I/O
P1[4]
Optional External Clock Input (EXTCLK).
18
I/O
P1[6]
19
Input
XRES
Active high external reset with internal pull
down.
20
I/O
I
P2[0]
Direct switched capacitor block input.
21
I/O
I
P2[2]
Direct switched capacitor block input.
22
I/O
P2[4]
External Analog Ground (AGND).
23
I/O
P2[6]
External Voltage Reference (VREF).
24
I/O
I
P0[0]
Analog column mux input.
25
I/O
I/O
P0[2]
Analog column mux input and column output.
26
I/O
I/O
P0[4]
Analog column mux input and column output.
27
I/O
I
P0[6]
Analog column mux input.
28
Power
Vdd
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
A, I,P0[7]
A,IO, P0[5]
A,IO, P0[3]
A,I, P0[1]
P2[7]
P2[5]
A,I, P2[3]
A, I,P2[1]
SMP
I2CSCL,P1[7]
I2CSDA,P1[5]
P1[3]
I2CSCL,XTALin,P1[1]
Vss
Vdd
P0[6], A,I
P0[4], A,IO
P0[2], A,IO
P0[0], A,I
P2[6],ExternalVREF
P2[4],ExternalAGND
P2[2], A,I
P2[0], A,I
XRES
P1[6]
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
PDIP
SSOP
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
