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ADC1413D065 Datasheet(PDF) 38 Page - NXP Semiconductors |
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ADC1413D065 Datasheet(HTML) 38 Page - NXP Semiconductors |
38 / 38 page NXP Semiconductors ADC1413D065/080/105/125 Dual 14 bits ADC; 65, 80, 105 or 125 Msps © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 June 2009 Document identifier: ADC1413D065_080_105_125_2 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Thermal characteristics. . . . . . . . . . . . . . . . . . . 6 9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 11 Clock and digital output timing . . . . . . . . . . . 10 11.1 Serial output timings . . . . . . . . . . . . . . . . . . . 10 12 SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Application information. . . . . . . . . . . . . . . . . . 12 13.1 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 12 13.1.1 Input stage description . . . . . . . . . . . . . . . . . . 12 13.1.2 Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 13 13.1.3 Transformer. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13.2 System reference and power management . . 14 13.2.1 Internal/external reference . . . . . . . . . . . . . . . 14 13.2.2 Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 16 13.2.3 Common-mode output voltage (VI(cm)) . . . . . . 17 13.2.4 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13.3 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.3.1 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.3.2 Equivalent input circuit . . . . . . . . . . . . . . . . . . 18 13.3.3 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 19 13.4 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 19 13.4.1 Serial output equivalent circuit . . . . . . . . . . . . 19 13.5 JESD204A serializer. . . . . . . . . . . . . . . . . . . . 20 13.5.1 Digital JESD204A formatter . . . . . . . . . . . . . . 20 13.5.2 ADC core output codes versus input voltage . 22 13.6 Serial Peripheral Interface (SPI) . . . . . . . . . . . 22 13.6.1 Register description . . . . . . . . . . . . . . . . . . . . 22 13.6.2 Channel control. . . . . . . . . . . . . . . . . . . . . . . . 23 13.6.3 Register description . . . . . . . . . . . . . . . . . . . . 25 13.6.4 JESD204A digital control registers . . . . . . . . . 27 13.6.5 Serial interface timings . . . . . . . . . . . . . . . . . . 34 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 35 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 36 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 37 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 37 16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 37 16.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 37 17 Contact information . . . . . . . . . . . . . . . . . . . . 37 18 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 |
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