TQ8016

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3

Figure 1. TQ8016 Architecture

Table 1. Pin Descriptions

Pin Name

Levels

Description

D0–D15

ECL

Differential Data Inputs

D0–D15

ECL

Differential Data Inputs

D0–D15

ECL

Differential Data Inputs

O0–O15

ECL

Differential Data Outputs

O0–O15

ECL

Differential Data Outputs

IA0–IA3

CMOS

Input Address

OA0–OA3

CMOS

Output Address

CONFIGURE

CMOS

Switch Reconfiguration

DATA

OUT 15

(O15)

5

RESET

OUTPUT

SELECT ADDRESS

(OA0:3)

Input

Buffers

DATA

OUT 0

(O0)

Configuration

Register

Program Register

CONFIGURE

LOAD

4

16 X 1-BIT

MULTIPLEXER

16 X 1-BIT

MULTIPLEXER

.

.

.

.

.

.

.

.

.

.

.

.

DATA IN 0

(I0)

DATA IN 15

(I15)

4

INPUT ADDRESS

(IA0:3)

4:16

DECODE