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ST7920 Datasheet(PDF) 7 Page - Sitronix Technology Co., Ltd.

Part No. ST7920
Description  Chinese Fonts built in LCD controller/driver
Download  49 Pages
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Manufacturer  SITRONIX [Sitronix Technology Co., Ltd.]
Direct Link  http://www.sitronix.com.tw
Logo SITRONIX - Sitronix Technology Co., Ltd.

ST7920 Datasheet(HTML) 7 Page - Sitronix Technology Co., Ltd.

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ST7920
V4.0
7/49
2008/08/18
Pin Description
Name
No.
I/O
Connects to
Function
XRESET
11
I
System reset input (low active).
PSB
23
I
Interface selection:
0: serial mode;
1: 8/4-bit parallel bus mode.
RS(CS*)
17
I
MPU
Parallel Mode: Register select.
0: Select instruction register (write)
or busy flag, address counter (read);
1: Select data register (write/read).
Serial mode: Chip select.
1: chip enabled;
0: chip disabled.
When chip is disabled, SID and SCLK
should be set as
“H” or “L”. Transcient
of SID and SCLK is not allowed.
RW(SID*)
18
I
MPU
Parallel Mode: Read/Write control.
0: Write;
1: Read.
Serial Mode: Sserial data input.
E(SCLK*)
19
I
MPU
Parallel Mode: 1: Enable trigger.
Serial Mode: Serial clock.
D4 to D7
28~31
I/O
MPU
Higher nibble data bus of 8-bit interface
and data bus for 4-bit interface
D0 to D3
24~27
I/O
MPU
Lower nibble data bus of 8-bit interface.
CL1
12
O
Extension segment drv.
Latch signal for extension segment
drivers.
CL2
13
O
Extension segment drv.
Shift clock for extension segment
drivers.
M
15
O
Extension segment drv.
AC signal for extension segment drivers
voltage inversion.
DOUT
16
O
Extension segment drv.
Data output for extension segment
drivers.
COM1 to
COM32
40~71
O
LCD
Common signals.
SEG1 to
SEG64
136~73
O
LCD
Segment signals.
V0 to V4
1~3,7,8
LCD bias voltage.
V0 ~ V4 ≦ 7V.
VDD
10,14
I
Power
VDD : 2.7V to 5.5V.
Vss
9,20
I
Power
VSS: 0V.
OSC1,
OSC2
21,22
I, O
Resistors
Using internal oscillator:
5.0V R=33K;
2.7V R=18K.
Using external clock:
Use OSC1 as external clock input.
VOUT
33
O
Resistors
LCD voltage doubler output.
VOUT ≦ 7V.
*Note: The OSC pin must have the shortest wiring pattern of all other pins. To prevent noise from other
signal lines, it should also be enclosed by the largest GND pattern. Poor anti-noise characteristics on the
OSC line will result in malfunction, or adversely affect the clock
’s duty ratio.


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