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ST7541 Datasheet(PDF) 63 Page - Sitronix Technology Co., Ltd. |
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ST7541 Datasheet(HTML) 63 Page - Sitronix Technology Co., Ltd. |
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63 / 78 page  ST7541 Ver 1.9 63/78 2007/9/3 Serial Interface (3-Line Interface) First bit Last bit Figure 32 (VDD=3.3V, Ta=–30~85°C) Rating Item Signal Symbol Condition Min. Max. Units Serial Clock Period tSCYC 50 — SCL “H” pulse width tSHW 25 — SCL “L” pulse width SCL tSLW 25 — Data setup time tSDS 20 — Data hold time SI tSDH 10 — CS-SCL time tCSS 20 — CS-SCL time CSB tCSH 40 — ns (VDD=2.7V, Ta=–30~85°C) Rating Item Signal Symbol Condition Min. Max. Units Serial Clock Period tSCYC 100 — SCL “H” pulse width tSHW 50 — SCL “L” pulse width SCL tSLW 50 — Data setup time tSDS 30 — Data hold time SI tSDH 20 — CS-SCL time tCSS 30 — CS-SCL time CSB tCSH 60 — ns (VDD=1.8V, Ta=–30~85°C) Rating Item Signal Symbol Condition Min. Max. Units Serial Clock Period tSCYC 200 — SCL “H” pulse width tSHW 80 — SCL “L” pulse width SCL tSLW 80 — Data setup time tSDS 60 — Data hold time SI tSDH 30 — CS-SCL time tCSS 40 — CS-SCL time CSB tCSH 100 — ns *1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard. |
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