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GA1088 Datasheet(PDF) 5 Page - TriQuint Semiconductor

Part # GA1088
Description  11-Output Configurable Clock Buffer
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Manufacturer  TRIQUINT [TriQuint Semiconductor]
Direct Link  http://www.triquint.com
Logo TRIQUINT - TriQuint Semiconductor

GA1088 Datasheet(HTML) 5 Page - TriQuint Semiconductor

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GA1088
5
For additional information and latest specifications, see our website: www.triquint.com
Symbol
Input Clock (REFCLK)
Test Conditions (Figure 3) 1
Min
Typ
Max
Unit
t CPWH
CLK pulse width HIGH
Figure 4
3
---
ns
t CPWL
CLK pulse width LOW
Figure 4
3
---
ns
t IR
Input rise time (0.8 V - 2.0 V)
2.0
ns
AC Characteristics
Notes: 1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V).
2. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because the input duty
cycle can vary while the output duty cycle is typically 50/50. The delay tPD is measured at the 1.5 V level between CLK and FBIN.
3. Skew specifies the width of the window in which outputs switch, and is measured at 1.5 V.
4. This specification represents the deviation from 50/50 on the outputs.
5. Jitter specifications refer to peak-to-peak value. tJR is the jitter on the output with respect to the reference clock. tJP is the jitter on the
output with respect to the output’s previous rising edge.
6. tSYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and a connection from one of the
outputs to FBIN.
Figure 3. AC Test Circuit
Notes:
Q0
Q1
Q2
Q10
FBIN
CLK
R1
R2
+5 V
R1
R2
+5 V
R1
R2
+5 V
R1
R2
+5 V
R1
R2
+5 V
Y
X
50
Z
Z
R1 = 160
R2 = 71
Y + Z = X
Symbol
Input Clock (Q0–Q10)
Test Conditions (Figure 3) 1
Min
Typ
Max
Unit
t OR,t OF
Rise/fall time (0.8 V – 2.0 V)
Figure 4
350
1400
ps
t PD1 2
CLK Î to FBIN Î (GA1088-MC500)
Figure 4
–850
–350
+150
ps
t PD2 2
CLK Î to FBIN Î (GA1088-MC700)
Figure 4
–1050
–350
+350
ps
t SKEW1 3
Rise–rise, fall–fall (within group)
Figure 5
60
150
ps
t SKEW2 3
Rise–rise, fall–fall (group-to-group, aligned) Figure 6 (skew2 takes into account skew1)
75
350
ps
t SKEW3 3 Rise–rise, fall–fall (group-to-group, non-aligned)Figure 7 (skew3 takes into account skews1, 2)
650
ps
t SKEW4 3
Rise-fall, fall-rise
Figure 8 (skew4 takes into account skew3)
1200
ps
t CYC 4
Duty-cycle Variation
Figure 4
–1000
0
+1000
ps
t JP 5
Period-to-Period Jitter
Figure 4
80
200
ps
t JR 5
Random Jitter
Figure 4
190
400
ps
t SYNC 6
Synchronization Time
10
500
µs
(VDD = +5 V + 5%, TA = 0 °C to +70 °C)


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