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ST2204 Datasheet(PDF) 18 Page - Sitronix Technology Co., Ltd.

Part No. ST2204
Description  8 BIT Integrated Microcontroller with 512K Bytes ROM
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Manufacturer  SITRONIX [Sitronix Technology Co., Ltd.]
Direct Link  http://www.sitronix.com.tw
Logo SITRONIX - Sitronix Technology Co., Ltd.

ST2204 Datasheet(HTML) 18 Page - Sitronix Technology Co., Ltd.

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ST2204
Ver 0.6
18/24
2008/11/10
1
15
5.. D
DIIR
RE
EC
CT
T M
ME
EM
MO
OR
RY
Y A
AC
CC
CE
ES
SS
S ((D
DM
MA
A))
To speed up the memory access of this system, a
sequential direct memory access (DMA) controller is
designed-in. DMA can perform memory transfer function
more efficient than CPU does. While DMA working, data
ROM register (DRR) will disable and DMA use DMA
memory bank register (DMR) to access ROM. After DMA
complete, ROM bank control still return to DRR.
With the help of DMR can make DMS across bank
boundary smoothly, but DMR is only valid for DMS. The
DMR can automatic increases when DMS across bank
boundary.
LCD
DMA
CPU
SRAM
ROM
LCD_CTL
FIGURE 15-1 System Block Diagram
1
16
6.. C
CL
LO
OC
CK
KIIN
NG
G O
OU
UT
TP
PU
UT
TS
S
Three clocking outputs PE0, PE1 and PE2 are supported by
the ST2204. These signals are very useful for outputs of high
frequency, such as PWM base signal or carrier of remote
control. Timer0, Timer1 overflow signals are clock sources for
PE0 and PE1, while BGRCK are for PE2.
Clocking Outputs: PE0 and PE1
Overflow states of Timers will be connected to toggle data of
PE[0:1]
when setting function selection bits TCO0/TCO1
(PMCR[0:1]). Meanwhile PE0/PE1 output clocked data of half
the frequency of Timers. After resetting TCO0/TCO1, the toggle
operation ceases. Then PE0/PE1 return to the original logic
level of PE[0:1].
Clocking Output: PE2
BGRCK will output through PE2 when setting function selection
bit BCO (PMCR[2]). If BCO is cleared, PE2 returns to the
original logic level of PE[2].


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