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ST2204 Datasheet(PDF) 17 Page - Sitronix Technology Co., Ltd.

Part No. ST2204
Description  8 BIT Integrated Microcontroller with 512K Bytes ROM
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Manufacturer  SITRONIX [Sitronix Technology Co., Ltd.]
Direct Link  http://www.sitronix.com.tw
Logo SITRONIX - Sitronix Technology Co., Ltd.

ST2204 Datasheet(HTML) 17 Page - Sitronix Technology Co., Ltd.

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ST2204
Ver 0.6
17/24
2008/11/10
1
14
4.. U
UN
NIIV
VE
ER
RS
SA
AL
L A
AS
SY
YN
NC
CH
HR
RO
ON
NO
OU
US
S R
RE
EC
CE
EIIV
VE
ER
R//T
TR
RA
AN
NS
SM
MIIT
TT
TE
ER
R
The ST2204 integrates one universal asynchronous
receiver/transmitter (UART), which can be used to
communicate with external serial devices. Serial data is
transmitted and received at standard bit rates using the
internal baud rate generator (BGR), which is controlled by
BGR control register BCTR. FIGURE 14-1 shows the block
diagram of UART.
CPU Interface
Baud Rate
Generator
Transmitter
Receiver
TXD0
RXD0
Serial
Interface
IrDA
Interface
TXD1
RXD1
FIGURE 14-1 UART Block Diagram
14.2 UART Operations
The UART has two modes of operation, NRZ and IrDA,
which represent data in different ways for serial
communication protocols, RS-232 and IrDA.
14.2.1 NRZ mode
The non-return to zero (NRZ) mode is primarily associated
with RS-232. Each character is transmitted as a frame
delimited by a start bit at the beginning and a stop bit at the
end. Data bits are transmitted least significant bit (LSB) first,
and each bit occupies a period of time equal to 1 full bit. If
parity is used, the parity bit is transmitted after the most
significant bit. Data settings including data length, stop bit
number and parity are controlled by bit fields in UCTR.
FIGURE 14-2 illustrates a character “S” in NRZ mode.
FIGURE 14-2 NRZ ASCII “S” with Odd Parity
14.2.2 IrDA mode
IrDA mode uses character frames as NRZ mode does, but,
instead of driving ones and zeros for a full bit-time period,
zeros are transmitted as three-sixteenth (or less) bit-time
pulses (which is selected by PW[1:0] (IRCTR[2:1]), and
ones remain low. The polarity of transmitted pulses and
expected receive pulses can be inverted so that a direct
connection can be made to external IrDA transceiver
modules that use active low pulses. This is controlled by
RXINV
and TXINV (IRCTR[7:6]). IrDA mode is enabled by
control bit IREN (IRCTR[0]). FIGURE 14-3 illustrates a
character “S’ in IrDA mode.
FIGURE 14-3 IrDA ASCII “S” with Odd Parity


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