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ST2204 Datasheet(PDF) 3 Page - Sitronix Technology Co., Ltd.

Part No. ST2204
Description  8 BIT Integrated Microcontroller with 512K Bytes ROM
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Manufacturer  SITRONIX [Sitronix Technology Co., Ltd.]
Direct Link  http://www.sitronix.com.tw
Logo SITRONIX - Sitronix Technology Co., Ltd.

ST2204 Datasheet(HTML) 3 Page - Sitronix Technology Co., Ltd.

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ST2204
Ver 0.6
3/24
2008/11/10
3
3.. S
SIIG
GN
NA
AL
L D
DE
ES
SC
CR
RIIP
PT
TIIO
ON
NS
S
TABLE 3-1 Signal Function Groups
Function Group
Pad No.
Designation
Description
Power
18, 55,
94
VCC , PVCC
VCC: Power supply for system
PVCC: Power supply for PSGO and PSGOB
Ground
23, 51,
52, 74
GND , PGND
GND: System power ground
PGND: Power ground for PSGO and PSGOB
System control
15,
26
50,80
1,81
28
RESET ,
LVR
/ICE1,
ICE2/3,
TEST1/2,
MMD/ CS0
RESET : Active low system reset signal input
LVR
/ICE1:
LVR
: Low voltage reset signal output, connect this pin to
RESET to make Low Voltage Reset function work.
ICE1
: ICE1 function when in ICE mode
TEST1/2, ICE2/3:
Leave them open when normal operation
MMD/CS0:
Memory modes selection pin
Normal mode:
Enable internal ROM.
MMD/ CS0 connects to GND.
Emulation mode:
Disable internal ROM.
MMD/ CS0 connects to chip-select pin of external ROM.
One resistor should be added between VCC and this pin.
After reset cycles, MMD/ CS0 changes to be an output, and
outputs signal CS0 .
Clock
16,
19~22
XMD,
XIO,OSCI
OSCXO,OSCXI, ,
XMD:
High frequency oscillator (OSC) mode selection input
Low:
Crystal mode. One crystal or resonator should be
connected between OSCI and XIO
High:
Resistor oscillator mode. One resistor should be
connected between OSCI and VCC
OSCXI, OSCXO:
Connect one 32768Hz crystal between these
two pins when using low frequency oscillator
72, 73
WR , RD
External memory R/W control signals
2~4,
85~93,
95~105
A[22:0]
External memory address bus
External memory
bus signals
75~79,
82~84
D[7:0]
External memory data bus
PSG/PWM DAC
53, 54
PSGO, PSGOB
PSG outputs. Connect to one buzzer or speaker
Keyboard scan
signal (return line)
24~25,
27,29~33
PA7~0
I/O port A
GPIO
34~41
PB7~0
I/O port B
Chip selects
64~69
1
~
CS5
/PD4~0,
CS6 /A23/PD5
I/O port D and chip-select outputs
UART
48, 49,
70, 71
RXD0/PC7,TXD0/PC6,
RXD1/PD7,TXD1/PD6
UART signals and I/Os
SPI
43~47
DATA_READY /PC5 ,
SS /PC4 , MOSI/PC3 ,
MISO/PC2 , SCK/PC1
SPI signals and I/Os


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