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MPC8548CVTAQG Datasheet(PDF) 35 Page - Freescale Semiconductor, Inc |
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MPC8548CVTAQG Datasheet(HTML) 35 Page - Freescale Semiconductor, Inc |
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35 / 144 page  MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6 Freescale Semiconductor 35 Enhanced Three-Speed Ethernet (eTSEC) Figure 15 shows the TBI receive AC timing diagram. Figure 15. TBI Receive AC Timing Diagram 8.2.5 TBI Single-Clock Mode AC Specifications When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant eTSEC interface. In single-clock TBI mode, when TBICON[CLKSEL] = 1, a 125-MHz TBI receive clock is supplied on the TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode, whereas for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied on the TSEC_GTX_CLK125 pin in all TBI modes. A summary of the single-clock TBI mode AC specifications for receive appears in Table 32. Table 32. TBI single-clock Mode Receive AC Timing Specification Parameter/Condition Symbol Min Typ Max Unit RX_CLK clock period tTRRX 7.5 8.0 8.5 ns RX_CLK duty cycle tTRRH/TRRX 40 50 60 % RX_CLK peak-to-peak jitter tTRRJ —— 250 ps Rise time RX_CLK (20%–80%) tTRRR —— 1.0 ns Fall time RX_CLK (80%–20%) tTRRF —— 1.0 ns RCG[9:0] setup time to RX_CLK rising edge tTRRDVKH 2.0 — — ns RCG[9:0] hold time to RX_CLK rising edge tTRRDXKH 1.0 — — ns TSEC n_RX_CLK1 RCG[9:0] tTRX tTRXH tTRXR tTRXF tTRDVKH TSEC n_RX_CLK0 tTRDXKH tTRDVKH tTRDXKH tSKTRX tTRXH Valid Data Valid Data |
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