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MPC8548CHXAQJ Datasheet(PDF) 63 Page - Freescale Semiconductor, Inc |
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MPC8548CHXAQJ Datasheet(HTML) 63 Page - Freescale Semiconductor, Inc |
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63 / 144 page  MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6 Freescale Semiconductor 63 High-Speed Serial Interfaces (HSSI) • The maximum average current requirement that also determines the common mode voltage range: — When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the following bullet for more detail), since the input is AC-coupled on-chip. — This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 to 16 mA (0–0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage at 400 mV. — If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50 Ω to SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip. • The input amplitude requirement: — This requirement is described in detail in the following sections. Figure 39. Receiver of SerDes Reference Clocks 15.2.2 DC Level Requirement for SerDes Reference Clocks The DC level requirement for the MPC8548E SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below: • Differential mode — The input amplitude of the differential clock must be between 400 and 1600 mV differential peak-peak (or between 200 and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing less than 800 mV and greater than 200 mV. This requirement is the same for both external DC-coupled or AC-coupled connection. — For external DC-coupled connection, as described in Section 15.2.1, “SerDes Reference Clock Receiver Characteristics,” the maximum average current requirements sets the requirement for Input Amp 50 Ω 50 Ω SD_REF_CLK SD_REF_CLK |
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