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MPC8548CHXAQGB Datasheet(PDF) 15 Page - Freescale Semiconductor, Inc |
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MPC8548CHXAQGB Datasheet(HTML) 15 Page - Freescale Semiconductor, Inc |
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15 / 144 page  MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6 Freescale Semiconductor 15 Input Clocks 4 Input Clocks This section discusses the timing for the input clocks. 4.1 System Clock Timing Table 5 provides the system clock (SYSCLK) AC timing specifications for the MPC8548E. 4.2 Real Time Clock Timing The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter specification. The minimum pulse width of the RTC signal should be greater than 2x the period of the CCB clock. That is, minimum clock high time is 2 × t CCB, and minimum clock low time is 2 × tCCB. There is no minimum RTC frequency; RTC may be grounded if not needed. Table 5. SYSCLK AC Timing Specifications At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV. Parameter/Condition Symbol Min Typ Max Unit Notes SYSCLK frequency fSYSCLK 16 — 133 MHz 1, 6, 7, 8 SYSCLK cycle time tSYSCLK 7.5 — 60 ns 6, 7, 8 SYSCLK rise and fall time tKH, tKL 0.6 1.0 1.2 ns 2 SYSCLK duty cycle tKHK/tSYSCLK 40 — 60 % 3 SYSCLK jitter — — — ± 150 ps 4, 5 Notes: 1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum operating frequencies.Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio settings. 2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter—short term and long term—and is guaranteed by design. 5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter. 6. This parameter has been adjusted slower according to the workaround for device erratum GEN 13. 7. For spread spectrum clocking. Guidelines are + 0% to –1% down spread at modulation rate between 20 and 60 kHz on SYSCLK. 8. System with operating core frequency less than 1200 MHz must limit SYSCLK frequency to 100 MHz maximum.. |
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