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MPC8548CVTAQHB Datasheet(PDF) 82 Page - Freescale Semiconductor, Inc |
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MPC8548CVTAQHB Datasheet(HTML) 82 Page - Freescale Semiconductor, Inc |
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82 / 144 page  MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6 82 Freescale Semiconductor Serial RapidIO transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need only comply with the transmitter output compliance mask when pre-emphasis is disabled or minimized. Figure 52. Transmitter Output Compliance Mask 17.7 Receiver Specifications LP-serial receiver electrical and timing specifications are stated in the text and tables of this section. Receiver input impedance shall result in a differential return loss better that 10 dB and a common mode return loss better than 6 dB from 100 MHz to (0.8) × (baud frequency). This includes contributions from on-chip circuitry, the chip package, and any off-chip components related to the receiver. AC coupling Table 61. Transmitter Differential Output Eye Diagram Parameters Transmitter Type VDIFFmin (mV) VDIFFmax (mV) A (UI) B (UI) 1.25 GBaud short range 250 500 0.175 0.39 1.25 GBaud long range 400 800 0.175 0.39 2.5 GBaud short range 250 500 0.175 0.39 2.5 GBaud long range 400 800 0.175 0.39 3.125 GBaud short range 250 500 0.175 0.39 3.125 GBaud long range 400 800 0.175 0.39 0 VDIFF min VDIFF max –VDIFF min –VDIFF max 0B 1-B 1 Time in UI A1-A |
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