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MPC8548CVTAQGA Datasheet(PDF) 73 Page - Freescale Semiconductor, Inc |
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MPC8548CVTAQGA Datasheet(HTML) 73 Page - Freescale Semiconductor, Inc |
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73 / 144 page  MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6 Freescale Semiconductor 73 PCI Express Figure 48. Minimum Transmitter Timing and Voltage Output Compliance Specifications 16.4.3 Differential Receiver (RX) Input Specifications Table 53 defines the specifications for the differential input at all receivers (RXs). The parameters are specified at the component pins. Table 53. Differential Receiver (RX) Input Specifications Symbol Parameter Min Nom Max Unit Comments UI Unit interval 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for spread spectrum clock dictated variations. See Note 1. VRX-DIFFp-p Differential peak-to-peak input voltage 0.175 — 1.200 V VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D–|. See Note 2. TRX-EYE Minimum receiver eye width 0.4 — — UI The maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as TRX-MAX-JITTER =1 – TRX-EYE = 0.6 UI. See Notes 2 and 3. TRX-EYE-MEDIAN-to- MAX-JITTER Maximum time between the jitter median and maximum deviation from the median — — 0.3 UI Jitter is defined as the measurement variation of the crossing points (VRX-DIFFp-p = 0 V) in relation to a recovered TX UI. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. See Notes 2, 3, and 7. VTX-DIFF = 0 mV (D+ D– Crossing Point) [De-Emphasized Bit] 0.07 UI = UI – 0.3 UI (JTX-TOTAL-MAX) 566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB) [Transition Bit] VTX-DIFFp-p-MIN = 800 mV VRX-DIFF = 0 mV (D+ D– Crossing Point) [Transition Bit] VTX-DIFFp-p-MIN = 800 mV |
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