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MPC8548CHXAQJA Datasheet(PDF) 42 Page - Freescale Semiconductor, Inc |
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MPC8548CHXAQJA Datasheet(HTML) 42 Page - Freescale Semiconductor, Inc |
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42 / 144 page  MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6 42 Freescale Semiconductor Local Bus Table 39 provides the DC electrical characteristics for the local bus interface operating at BVDD =2.5 VDC. 10.2 Local Bus AC Electrical Specifications Table 40 describes the timing parameters of the local bus interface at BVDD = 3.3 V. For information about the frequency range of local bus, see Section 19.1, “Clock Ranges.” Table 39. Local Bus DC Electrical Characteristics (2.5 V DC) Parameter Symbol Min Max Unit High-level input voltage VIH 1.70 BVDD + 0.3 V Low-level input voltage VIL –0.3 0.7 V Input current (VIN 1 = 0 V or V IN = BVDD)IIH —10 μA IIL –15 High-level output voltage (BVDD = min, IOH = –1 mA) VOH 2.0 — V Low-level output voltage (BVDD = min, IOL = 1 mA) VOL —0.4 V Note: 1. Note that the symbol VIN, in this case, represents the BVIN symbol referenced in Table 1 and Table 2. Table 40. Local Bus Timing Parameters (BVDD = 3.3 V)—PLL Enabled Parameter Symbol1 Min Max Unit Notes Local bus cycle time tLBK 7.5 12 ns 2 Local bus duty cycle tLBKH/tLBK 43 57 % — LCLK[n] skew to LCLK[m] or LSYNC_OUT tLBKSKEW — 150 ps 7, 8 Input setup to local bus clock (except LGTA/LUPWAIT) tLBIVKH1 1.8 — ns 3, 4 LGTA/LUPWAIT input setup to local bus clock tLBIVKH2 1.7 — ns 3, 4 Input hold from local bus clock (except LGTA/LUPWAIT) tLBIXKH1 1.0 — ns 3, 4 LGTA/LUPWAIT input hold from local bus clock tLBIXKH2 1.0 — ns 3, 4 LALE output transition to LAD/LDP output transition (LATCH hold time) tLBOTOT 1.5 — ns 6 Local bus clock to output valid (except LAD/LDP and LALE) tLBKHOV1 —2.0 ns — Local bus clock to data valid for LAD/LDP tLBKHOV2 —2.2 ns 3 Local bus clock to address valid for LAD tLBKHOV3 —2.3 ns 3 Local bus clock to LALE assertion tLBKHOV4 —2.3 ns 3 Output hold from local bus clock (except LAD/LDP and LALE) tLBKHOX1 0.7 — ns 3 Output hold from local bus clock for LAD/LDP tLBKHOX2 0.7 — ns 3 Local bus clock to output high Impedance (except LAD/LDP and LALE) tLBKHOZ1 —2.5 ns 5 |
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