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SPC5604PEF0MLQ7R Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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SPC5604PEF0MLQ7R Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
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3 / 84 page  MPC5604P Microcontroller Data Sheet, Rev. 5 Preliminary—Subject to Change Without Notice Freescale Semiconductor 3 1 Overview This document provides electrical specifications, pin assignments, and package diagrams for the MPC5604P series of microcontroller units (MCUs). For functional characteristics, refer to the MPC5604P Microcontroller Reference Manual. MPC5604P microcontrollers are members of a new family of next generation microcontrollers built on the Power Architecture™. This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the devices. The MPC5604P family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding range of automotive-focused products designed to address electrical hydraulic power steering (EHPS), electric power steering (EPS) and airbag applications. The advanced and cost-efficient host processor core of the MPC5604P automotive controller family complies with the Power Architecture embedded category, which is 100 percent user-mode compatible with the original PowerPC user instruction set architecture (UISA). It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. 1.1 Device comparison Table 1 provides a summary of different members of the MPC5604P family and their features to enable a comparison among the family members and an understanding of the range of functionality offered within this family. Table 1. MPC5604P device comparison Feature MPC5603P MPC5604P Code Flash memory (with ECC) 384 KB 512 KB Data Flash / EE (with ECC) 64 KB 64 KB RAM (with ECC) 36 KB 40 KB Processor core 32-bit e200z0h Instruction set VLE CPU performance 0–64 MHz FMPLL (frequency-modulated phase-locked loop) modules 2 INTC (interrupt controller) channels 147 PIT (periodic interrupt timer) 1 (includes four 32-bit timers) Enhanced DMA (direct memory access) channels 16 FlexRay Yes1 FlexCAN (controller area network) 22,3 Safety port Yes (via second FlexCAN module) FCU (fault collection unit) Yes CTU (cross triggering unit) Yes eTimer channels 2 × 6 FlexPWM (pulse-width modulation) channels 8 Analog-to-digital converters (ADC) Two (10-bit, 16-channel) LINFlex modules 2 DSPI (deserial serial peripheral interface) modules 4 |
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