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MC9328MX21CJM Datasheet(PDF) 87 Page - Freescale Semiconductor, Inc |
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MC9328MX21CJM Datasheet(HTML) 87 Page - Freescale Semiconductor, Inc |
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87 / 100 page  Specifications MC9328MX21 Technical Data, Rev. 3.3 Freescale Semiconductor 87 3.20 DTACK Mode Memory Access Timing Diagrams When enabled, the DTACK input signal is used to externally terminate a data transfer. For DTACK enabled operations, a bus time-out monitor generates a bus error when an external bus cycle is not terminated by the DTACK input signal after 1024 HCLK clock cycles have elapsed, where HCLK is the internal system clock driven from the PLL module. For a 133 MHz HCLK setting, this time equates to 7.7 μs. Refer to the Section 3.5, “DPLL Timing Specifications” for more information on how to generate different HCLK frequencies. There are two modes of operation for the DTACK input signal: rising edge detection or level sensitive detection with a programmable insensitivity time. DTACK is only used during external asynchronous data transfers, thus the SYNC bit in the chip select control registers must be cleared. During edge detection mode, the EIM will terminate an external data transfer following the detection of the DTACK signal’s rising edge, so long as it occurs within the 1024 HCLK cycle time. Edge detection mode is used for devices that follow the PCMCIA standard. Note that DTACK rising edge detection mode can only be used for CS[5] operations. To configure CS[5] for DTACK rising edge detection, the following bits must be programmed in the Chip Select 5 Control Register and EIM Configuration Register: • WSC bit field set to 0x3F and CSA (or CSN) set to 1 or greater in the Chip Select 5 Control Register • AGE bit set in the EIM Configuration Register Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements of the external device. The requirement of setting CSA or CSN is required to allow the EIM to wait for the rising edge of DTACK during back-to-back external transfers, such as during DMA transfers or an internal 32-bit access through an external 16-bit data port. During level sensitive detection, the EIM will first hold off sampling the DTACK signal for at least 2 HCLK cycles, and up to 5 HCLK cycles as programmed by the DCT bits in the Chip Select Control Register. After this insensitivity time, the EIM will sample DTACK and if it detects that DTACK is logic high, it will continue the data transfer at the programmed number of wait states. However, if the EIM detects that DTACK is logic low, it will wait until DTACK goes to logic high to continue the access, so long as this occurs within the 1024 HCLK cycle time. If at anytime during an external data transfer DTACK goes to logic low, the EIM will wait until DTACK returns to logic high to resume the data transfer. Level detection is often used for asynchronous devices such graphic controller chips. Level detection may be used with any chip select except CS[4] as it is multiplexed with the DTACK signal. To configure a chip select for DTACK level sensitive detection, the following bits must be programmed in the Chip Select Control Register and EIM Configuration Register: • EW bit set, WSC set to > 1, and CSN set to < 3 in the Chip Select Control Register • BCD/DCT set to desired “insensitivity time” in the Chip Select Control Register. The “insensitivity time” is dictated by the external device’s timing requirements. • AGE bit cleared in the EIM Configuration Register Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements of the external device. The waveforms in the following section provide examples of the DTACK signal operation. |
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