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MC9328MX21CJM Datasheet(PDF) 57 Page - Freescale Semiconductor, Inc |
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MC9328MX21CJM Datasheet(HTML) 57 Page - Freescale Semiconductor, Inc |
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57 / 100 page  Specifications MC9328MX21 Technical Data, Rev. 3.3 Freescale Semiconductor 57 3.17 1-Wire Interface Timing 3.17.1 Reset Sequence with Reset Pulse Presence Pulse To begin any communications with the DS2502, it is required that an initialization procedure be issued. A reset pulse must be generated and then a presence pulse must be detected. The minimum reset pulse length is 480 us. The bus master (one-wire) will generate this pulse, then after the DS2502 detects a rising edge on the one-wire bus, it will wait 15-60 us before it will transmit back a presence pulse. The presence pulse will exist for 60-240 us. The timing diagram for this sequence is shown in Figure 46. Figure 46. 1-Wire Initialization The reset pulse begins the initialization sequence and it is initiated when the RPP control register bit is set. When the presence pulse is detected, this bit will be cleared. The presence pulse is used by the bus master to determine if at least one DS2502 is connected. Software will determine if more than one DS2502 exists. The one-wire will sample for the DS2502 presence pulse. The presence pulse is latched in the one-wire 28 (Tx) CK high to STXD high impedance 9.02 16.46 7.29 14.97 ns 29 SRXD setup time before (Rx) CK low 1.49 – 1.49 – ns 30 SRXD hole time after (Rx) CK low 0 – 0 – ns Synchronous Internal Clock Operation (SSI3 Ports) 31 SRXD setup before (Tx) CK falling 21.99 – 21.99 – ns 32 SRXD hold after (Tx) CK falling 0–0– ns Synchronous External Clock Operation (SSI3 Ports) 33 SRXD setup before (Tx) CK falling 3.80 – 3.80 – ns 34 SRXD hold after (Tx) CK falling 0–0– ns 1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. Table 37. SSI to SSI3 Ports Timing Parameters (Continued) Ref No. Parameter 1.8 V ± 0.1 V 3.0 V ± 0.3 V Unit Minimum Maximum Minimum Maximum one-wire DS2502 waits 15-60us DS2502 Tx “presence pulse” 60-240us 68us BUS Reset and Presence Pulses One-Wire samples (set PST) 512us AutoClear RPP Control Bit Set RPP 511 us |
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