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MC9328MX21CJM Datasheet(PDF) 38 Page - Freescale Semiconductor, Inc |
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MC9328MX21CJM Datasheet(HTML) 38 Page - Freescale Semiconductor, Inc |
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38 / 100 page  MC9328MX21 Technical Data, Rev. 3.3 38 Freescale Semiconductor Specifications Figure 28. Timing Diagrams at Data Read Figure 29 shows the basic write operation timing. As with the read operation, after the card response, the data transfer starts after NWR cycles. The data is suffixed with CRC check bits to allow the card to check for transmission errors. The card sends back the CRC check result as a CC status token on the data line. If there was a transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC status (010) is returned. The card expects a continuous flow of data blocks if it is configured to multiple block mode, with the flow terminated by a stop transmission command. NAC cycles Read Data Timing of single block read NAC cycles Read Data Timing of multiple block read NAC cycles NST Timing of stop command (CMD12, data transfer mode) Host Command Response NCR cycles CMD Content S T E Z Z P P S T Content CRC E Z ****** CRC DAT Z****Z Z Z P P S D ***** D D D DAT Z****Z Z Z P P S D ***** ****** D D D P ***** P S D D D D ****** Host Command Response NCR cycles CMD Content S T E Z Z P P S T Content CRC E Z ****** CRC ***** Read Data Host Command Response NCR cycles CMD Content S T E Z Z P P S T Content CRC E Z ****** CRC Valid Read Data DAT ***** Z Z E ***** D D D D D D D D Z |
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