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MC9328MX21VK Datasheet(PDF) 12 Page - Freescale Semiconductor, Inc |
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MC9328MX21VK Datasheet(HTML) 12 Page - Freescale Semiconductor, Inc |
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12 / 100 page  MC9328MX21 Technical Data, Rev. 3.3 12 Freescale Semiconductor Signal Descriptions SD2_CMD SD Command bidirectional signal. This signal is multiplexed with SLCDC1_CS signal from SLCDC1. SD2_CLK SD Output Clock signal. This signal is multiplexed with SLCDC1_CLK signal from SLCDC1. SD2_D[3:0] SD Data bidirectional signals. SD2_D[3:2] are multiplexed with SLCDC1_RS and SLCDC_D0 signals from SLCDC1. UARTs – IrDA/Auto-Bauding UART1_RXD Receive Data input signal UART1_TXD Transmit Data output signal UART1_RTS Request to Send input signal UART1_CTS Clear to Send output signal UART2_RXD Receive Data input signal. This signal is multiplexed with KP_ROW6 signal from KPP. UART2_TXD Transmit Data output signal. This signal is multiplexed with KP_COL6 signal from KPP. UART2_RTS Request to Send input signal. This signal is multiplexed with KP_ROW7 signal from KPP. UART2_CTS Clear to Send output signal. This signal is multiplexed with KP_COL7 signal from KPP. UART3_RXD Receive Data input signal. This signal is multiplexed with IR_RXD from FIRI. UART3_TXD Transmit Data output signal. This signal is multiplexed with IR_TXD from FIRI. UART3_RTS Request to Send input signal UART3_CTS Clear to Send output signal UART4_RXD Receive Data input signal which is multiplexed with USBH1_RXDP and USBH1_TXDP. UART4_TXD Transmit Data output signal which is multiplexed with USBH1_TXDM. UART4_RTS Request to Send input signal which is multiplexed with USBH1_FS and USBH1_RXDP. UART4_CTS Clear to Send output signal which is multiplexed with USBH1_TXDP and USBH1_RXDM. Serial Audio Port – SSI (configurable to I2S protocol and AC97) SSI1_CLK Serial clock signal which is output in master or input in slave SSI1_TXD Transmit serial data SSI1_RXD Receive serial data SSI1_FS Frame Sync signal which is output in master and input in slave SYS_CLK1 SSI1 master clock. Multiplexed with TOUT. SSI2_CLK Serial clock signal which is output in master or input in slave. SSI2_TXD Transmit serial data signal SSI2_RXD Receive serial data SSI2_FS Frame Sync signal which is output in master and input in slave. SYS_CLK2 SSI2 master clock. Multiplexed with TOUT. SSI3_CLK Serial clock signal which is output in master or input in slave. Multiplexed with SLCDC2_CLK SSI3_TXD Transmit serial data signal which is multiplexed with SLCDC2_CS SSI3_RXD Receive serial data which is multiplexed with SLCDC2_RS SSI3_FS Frame Sync signal which is output in master and input in slave. Multiplexed with SLCDC2_D0. SAP_CLK Serial clock signal which is output in master or input in slave. Table 2. i.MX21 Signal Descriptions (Continued) Signal Name Function/Notes |
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