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MC9S08QG8MDNE Datasheet(PDF) 67 Page - Freescale Semiconductor, Inc |
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MC9S08QG8MDNE Datasheet(HTML) 67 Page - Freescale Semiconductor, Inc |
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67 / 314 page  Chapter 5 Resets, Interrupts, and General System Control MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 65 5.6 Low-Voltage Detect (LVD) System The MC9S08QG8/4 includes a system to protect against low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and a LVD circuit with a user selectable trip voltage, either high (VLVDH) or low (VLVDL). The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip voltage is selected by LVDV in SPMSC3. The LVD is disabled upon entering any of the stop modes unless LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then the MCU cannot enter stop1 or stop2, and the current consumption in stop3 with the LVD enabled will be greater. 5.6.1 Power-On Reset Operation When power is initially applied to the MCU, or when the supply voltage drops below the VPOR level, the POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above the VLVDL level. Both the POR bit and the LVD bit in SRS are set following a POR. 5.6.2 LVD Reset Operation The LVD can be configured to generate a reset upon detection of a low voltage condition by setting LVDRE to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the level determined by LVDV. The LVD bit in the SRS register is set following either an LVD reset or POR. 5.6.3 LVD Interrupt Operation When a low voltage condition is detected and the LVD circuit is configured using SPMSC1 for interrupt operation (LVDE set, LVDIE set, and LVDRE clear), then LVDF in SPMSC1 will be set and an LVD interrupt request will occur. 5.6.4 Low-Voltage Warning (LVW) The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is approaching, but is above, the LVD voltage. The LVW does not have an interrupt associated with it. There are two user selectable trip voltages for the LVW, one high (VLVWH) and one low (VLVWL). The trip voltage is selected by LVWV in SPMSC3. 5.7 Real-Time Interrupt (RTI) The real-time interrupt function can be used to generate periodic interrupts. The RTI can accept two sources of clocks, the 1-kHz internal clock or an external clock if available. External clock input requires the XOSC module; consult Table 1-1 to see if your MCU contains this module. The RTICLKS bit in SRTISC is used to select the RTI clock source. Either RTI clock source can be used when the MCU is in run, wait or stop3 mode. When using the external oscillator in stop3, it must be enabled in stop (EREFSTEN = 1) and configured for low frequency operation |
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