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MC9S08QG8CDNE Datasheet(PDF) 39 Page - Freescale Semiconductor, Inc |
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MC9S08QG8CDNE Datasheet(HTML) 39 Page - Freescale Semiconductor, Inc |
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39 / 314 page  Chapter 3 Modes of Operation MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 37 3.6.3 Stop1 Mode Stop1 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most of the internal circuitry of the MCU is powered off in stop1, providing the lowest possible standby current. Upon entering stop1, all I/O pins automatically transition to their default reset states. Exit from stop1 is performed by asserting the wake-up pin (PTA5) on the MCU. NOTE PTA5/IRQ/TCLK/RESET always functions as an active-low wakeup input when the MCU is in stop2, regardless of how the pin is configured before entering stop2. The pullup is not automatically enabled. To use the internal pullup, set the PTAPE5 bit in the PTAPE register In addition, the real-time interrupt (RTI) can wake the MCU from stop1 if enabled. Upon wake-up from stop1 mode, the MCU starts up as from a power-on reset (POR): • All module control and status registers are reset • The LVD reset function is enabled and the MCU remains in the reset state if VDD is below the LVD trip point (low trip point selected due to POR) • The CPU takes the reset vector In addition to the above, upon waking up from stop1, the PDF bit in SPMSC2 is set. This flag is used to direct user code to go to a stop1 recovery routine. PDF remains set until a 1 is written to PPDACK in SPMSC2. 3.6.4 On-Chip Peripheral Modules in Stop Modes When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.3, “Stop1 Mode,” Section 3.6.2, “Stop2 Mode,” and Section 3.6.1, “Stop3 Mode,” for specific information on system behavior in stop modes. Table 3-2. Stop Mode Behavior Peripheral Mode Stop1 Stop2 Stop3 CPU Off Off Standby RAM Off Standby Standby FLASH Off Off Standby Parallel Port Registers Off Off Standby ADC Off Off Optionally On1 ACMP Off Off Standby ICS Off Off Optionally On2 IIC Off Off Standby |
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